Kerntopf Gate and Regular Structures for Symmetric Functions

1. Kerntopf Gate and Regular Structures for Symmetric Functions

2. Kerntopf Gate • The Kerntopf gate is described by equations: P = 1 @ A @ B @ C @ AB, Q = 1 @ AB @ B @ C @ BC, R = 1 @ A @ B @ AC. • When C=1 then P = A + B, Q = A * B, R = !B, so AND/OR gate is realized on outputs P and Q with C as the controlling input value. • When C = 0 then P = !A * ! B, Q = A + !B, R = A @ B. Despite theoretical advantages of Kerntopf gate over classical Fredkin and Toffoli gates, so far there are no published results on optical or CMOS realizations of this gate.

3. A B 0 1 >= >= MIN(A,B) Min/max gate Max/min gate MAX(A,B) Use of two Multi-valued Fredkin (Picton) Gates to create MIN/MAX gate Two garbage outputs for MIN/MAX cells using Picton Gate MIN(A,B) MAX(A,B) MAX(A,B) = A + B MIN(A,B) = A*B

4. Regular Structure for Symmetric Functions C S 1,2,3(A,B,C) Single Index symmetric functions A Unate interval symmetric functions MAX(A,B) =A+B Max/Min gate Max/Min gate Max/Min gate B C(A+B) S 1(A,B,C) MIN(A,B) inputs =A*B regular,simple S 2,3(A,B,C) C 0 1 EXOR level Regular symmetric structure EXOR level AB S 3(A,B,C) 0 1 00 01 11 10 S 2(A,B,C) 1 2 2 3 1 2 outputs regular regular Every single index Symmetric Function can be created by EXOR-ing last level gates of the previous regular expansion structure Indices of symmetric binary functions of 3 variables

5. D MAX(A,B,C,D) = A+B+C+D = S 1,2,,3,4(A,B,C) C MAX(A,B,C) = (A+B)+C = S 1,2,3(A,B,C) A MAX(A,B) =A+B B C(A+B) MIN(A,B) MIN(A,B) =A*B S 2,3(A,B,C) = (A*B) + C(A+B) S,2.3.4(A,B,C,D) Max/Min gate Max/Min gate Max/Min gate Max/Min gate Max/Min gate Max/Min gate MIN(A,B,C) = (A*B)*C = S 3(A,B,C) S 3,4(A,B,C,D) MIN(A,B,C,D) = A*B*C*D = S 4(A,B,C,D) Example for four variables, EXOR level added S 1(A,B,C,D) S 2(A,B,C,D) Every Binary Symmetric Function can be composed of MIN/MAX gates: Example for three variables S 3(A,B,C,D) S 4(A,B,C,D) It is obvious that any multi-output function can be created by OR-ing the outputs of EXOR level

6. D MAX(A,B,C,D) = A+B+C+D = S 1,2,,3,4(A,B,C) C MAX(A,B,C) = (A+B)+C = S 1,2,3(A,B,C) A MAX(A,B) =A+B B C(A+B) MIN(A,B) MIN(A,B) =A*B S 2,3(A,B,C) = (A*B) + C(A+B) S,2.3.4(A,B,C,D) Max/Min gate Max/Min gate Max/Min gate Max/Min gate Max/Min gate Max/Min gate MIN(A,B,C) = (A*B)*C = S 3(A,B,C) S 3,4(A,B,C,D) MIN(A,B,C,D) = A*B*C*D = S 4(A,B,C,D) Now we extend to Reversible Logic S 1(A,B,C,D) S 2,3,4(A,B,C,D) S 2(A,B,C,D) S 3,4(A,B,C,D) S 3(A,B,C,D) S 4(A,B,C,D) Denotes Feynman (controlled NOT) gate Denotes fan-out gate

7. Using Kerntopf and Feynman Gates in Reversible Programmable Gate Array RPGA Kerntopf Feynman Arbitrary symmetric function can be created by exoring single indices

8. Generalizations and Current Work • Arbitrary symmetric function can be realized in a net without repeated variables. • Arbitrary (non-symmetric) function can be realized in a net with repeated variables (so-called symmetrization). • Many non-symmetric functions can be realized in a net without repeated variables. • We work on the characterization of the functions realizable in these structures without repetitions and respective synthesis algorithms. Very many new circuit types, which are reversible and multi-valued generalizations of Shannon Lattices, Kronecker Lattices, and other regular structures introduced in the past. • Layout-driven synthesis to regular structures • CMOS, Optical, Quantum dot technologies. • Software

9. What to remember? • How to create systematically a structure to realize arbitrary symmetric function of a single output variable? • How to create systematically a structure to realize arbitrary multi-output symmetric function? • Draw a circuit with no garbages, similar to the circuit from two slides earlier, by adding mirror circuits. This circuit will have constant outputs so can be used as an oracle in Grover algorithm.