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Fast A/D sampler Mid semester presentation

Presented By: Tal Goihman , Irit Kaufman Instructor: Mony Orbach Spring 2011. Fast A/D sampler Mid semester presentation. Goals. Project Goal: Sample with FMC125 to PC memory @ highest possible speed Semester A Goal:

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Fast A/D sampler Mid semester presentation

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  1. Presented By: Tal Goihman, Irit Kaufman Instructor: MonyOrbach Spring 2011 Fast A/D sampler Mid semester presentation

  2. Goals • Project Goal: • Sample with FMC125 to PC memory @ highest possible speed • Semester A Goal: • Sample with FMC125 to DDR3 memory on the ML605 virtex6 development board

  3. Background • FMC125 Input options: • Single channel @ 5Gsps • Dual channel @ 2.5Gsps • Quad channel @ 1.25Gsps • Output - Sampled data available on: • ML605 On-board DDR3 • PC Memory & file system - through PCI-E (to be implemented next semester)

  4. Block Diagram

  5. Block Diagram: Main Data Channel • FMC125 to DDR3 • Data flows using a proprietary bus from the FMC125 to an AXI Master. • The AXI Master organizes the data received and sends it over the AXI bus to the AXI Slave interface of the Memory Controller. • The memory controller handles the transactions to DDR3.

  6. Block Diagram: MicroBlaze • MicroBlaze is a soft-core processor by Xilinx. • Function • Receive commands from PC using UART and control the FMC125 board through • Provide easy verification of the main channel by reading memory to UART. • Provide easy access to peripherals (Timer, LEDs, switches, etc.)

  7. AXI Bus background • Xilinx has adopted AXI bus, which is a standard bus protocol from ARM. • Characteristics • Memory mapped • Variable width, clock & burst length over a single bus.

  8. AXI write example

  9. Accomplished so far • Studying Xilinx Environment: ISE, XPS, SDK, Chipscope and Impact. • Getting familiar with ML605 board: hardware design, software examples. • Studying MIG • Running MIG example design. • Studying FMC125 • FMC125 functionality demonstration.

  10. A/D Sampler The FMC125 is a Quad-Channel ADC that provides four 8-bit ADC channels enabling simultaneous sampling of 1, 2, or 4 channels @ 5 , 2.5 , 1.25Gsps respectively. • So far: Ran example design and got samples from all 4 channels. • Problems: • 4DSP has reference design only for 4ch @ 1.25Gsps. • Reference design for 1ch @ 5Gsps available on July and priced at 2300 EU. • Cables are SSMC (already ordered)

  11. Main Data Channel • So far: • throughput of AXI Bus is 6400 MB/s matched to DDR3 throughput

  12. Test Environment • Verification of sampled data on DDR3 is accomplished by SW on MicroBlaze comparing read data with written pattern

  13. Additional Progress • Built all of the above block diagram excluding FMC125 connection to the system. • have a working AXI Master that actually writes a pattern to memory. • Have SW running on MicroBlaze that verified the written data successfully.

  14. Timeline

  15. Questions?Thanks

  16. Backup • Documantaion

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