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CS 230: Computer Organization and Assembly Language

CS 230: Computer Organization and Assembly Language. Aviral Shrivastava. Department of Computer Science and Engineering School of Computing and Informatics Arizona State University. Slides courtesy: Prof. Yann Hang Lee, ASU, Prof. Mary Jane Irwin, PSU, Ande Carle, UCB. Announcements.

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CS 230: Computer Organization and Assembly Language

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  1. CS 230: Computer Organization and Assembly Language Aviral Shrivastava Department of Computer Science and Engineering School of Computing and Informatics Arizona State University Slides courtesy: Prof. Yann Hang Lee, ASU, Prof. Mary Jane Irwin, PSU, Ande Carle, UCB

  2. Announcements • Important announcements will be made at the beginning of the lecture • Blackboard is setup • If you cannot access, let me know immediately • Make it an interactive forum • Lectures • Will be fast paced, so read before and after the class • Stop me as soon as you have a question, or you do not understand. • Realize that it is your last chance • Learning is your prerogative • I will skip some things that are in the textbook, and will teach somethings that are not in the textbook • Now you are in college

  3. More Announcements • Green card in front of the book • Take out half an hour to browse through it • MARS – MIPS Simulator • Write programs in MIPS assembly language • Is needed for projects 1 and 2 • Start playing with MARS • Quiz will be 45 mins • open book and notes • One question will be difficult • Quiz 1 • Thursday Sept 10, 2009. • Arithmetic, Load/Store and Branch Instructions

  4. The Instruction Set Architecture (ISA) software instruction set architecture hardware ISA - The interface description separating the software and hardware.

  5. Below the Program High-level language program (in C) swap (int v[], int k) . . . Assembly language program (for MIPS) swap: sll $2, $5, 2 add $2, $4, $2 lw $15, 0($2) lw $16, 4($2) sw $16, 0($2) sw $15, 4($2) jr $31 Machine (object) code (for MIPS) 000000 00000 00101 0001000010000000 000000 00100 00010 0001000000100000 100011 00010 01111 0000000000000000 100011 00010 10000 0000000000000100 101011 00010 10000 0000000000000000 101011 00010 01111 0000000000000100 000000 11111 00000 0000000000001000 C - Compiler Assembler

  6. Higher-Level Languages • Higher-level languages • Allow the programmer to think in a more natural language • Customized for their intended use, e.g., • Fortran for scientific computation • Cobol for business programming • Lisp for symbol manipulation • Improve programmer productivity and maintainability • more understandable code that is easier to debug and validate • Independent of • Computer on which it applications are developed • Computer on which it applications will execute • Enabler • Optimizing Compiler Technology • Very little programming at the assembler level

  7. MIPS R3000 Instruction Set Architecture Registers • Instruction Categories • Arithmetic • Load/Store • Jump and Branch • Floating Point • coprocessor • Memory Management • Special R0 - R31 PC HI LO 3 Instruction Formats: all 32 bits wide rs rt OP rd sa funct rs OP rt immediate jump target OP

  8. RISC Vs. CISC • MIPS ISA is a RISC ISA • RISC – Reduced Instruction Set Computer • CISC – Complex Instruction Set Computer • Many differences • Will learn over the lectures • One main difference • In MIPS (a RISC architecture), all instructions are 32-bits • In IA32 (a CISC architecture), instructions can be of variable widths

  9. MIPS ISA: Arithmetic Instructions • MIPS assembly language arithmetic statement add $t0, $s1, $s2 sub $t0, $s1, $s2 • Each arithmetic instruction performs only one operation • Each arithmetic instruction specifies exactly three operands destination  source1 op source2 • All operands are contained in the Register File • $t0, $s1,$s2 are in Register File • Operand order is fixed

  10. Compiling More Complex Statements • What is the assembler equivalent of h = (b - c) + d • Assume • Variable b is stored in register $s1 • Variable c is stored in $s2 • Variable d is stored in $s3 • Result is to be left in $s0 sub $t0, $s1, $s2 add $s0, $t0, $s3 ## $t0 = b - c ## $s0 = $t0 + d

  11. MIPS Register File Register File 5 5 5 32 32 32 src1 addr src1 data src2 addr 32 locations dst addr src2 data write data 32 bits • All source operands of arithmetic instructions must be from the Register File • All the destination operands of arithmetic instructions must be written into the Register File • Register File • Holds thirty-two 32-bit registers • Two read ports and • One write port • Registers are • Faster than main memory • Easier for a compiler to use • e.g., (A*B) – (C*D) – (E*F) can do multiplies in any order vs. stack • Can hold variables so that • code density improves (since register are named with fewer bits than a memory location) • Register addresses are indicated by using $

  12. Register Naming Convention 0 $zero constant 0 (Hardware) 1 $at reserved for assembler 2 $v0 expression evaluation & 3 $v1 function results 4 $a0 arguments 5 $a1 6 $a2 7 $a3 8 $t0 temporary: caller saves . . . (callee can clobber) 15 $t7 16 $s0 callee saves . . . (caller can clobber) 23 $s7 24 $t8 temporary (cont’d) 25 $t9 26 $k0 reserved for OS kernel 27 $k1 28 $gp pointer to global area 29 $sp stack pointer 30 $fp frame pointer 31 $ra return address (Hardware)

  13. MIPS ALU 32-bit 32-bit ALU 32-bit • 32-bit ALU • 2 32-bit sources • 1 32-bit result • Operations • Arithmetic • ADD, SUB, ... • Logical • AND, OR, NOR, XOR, …

  14. How does it work? Register File R0 R1 src1 reg no 17 R8 15 src1 data sub $t0, $s1, $s2 src2 reg no 25 R17 25 18 R18 10 dst addr src2 data 8 10 write data 15 R31 $s1  R17 25 $t0  R8 $s2  R18 10 - • Arithmetic instructions can only change the contents of the Register File • In CISC processors, arithmetic instructions are much more powerful – they can read and change the contents of the memory 15

  15. MIPS R3000 Instruction Set Architecture Registers • Instruction Categories • Arithmetic • Load/Store • Jump and Branch • Floating Point • coprocessor • Memory Management • Special R0 - R31 PC HI LO • 3 Instruction Formats: all 32 bits wide rs rt OP rd sa funct rs OP rt immediate jump target OP

  16. Memory • Arithmetic instructions operands must be registers • How do we get data into and out of memory? • Remember, program and data reside in memory (Not in registers) • What about programs with a lot of variables? Processor Devices Control Input Memory Datapath Output

  17. Accessing Memory 28 • MIPS has two basic data transfer instructions for accessing memory lw $t0, 4($s3) #load word from memory sw $t0, 8($s3) #store word to memory (assume $s3 holds 2410) • The data transfer instruction must specify • Memory address • where in memory to read from (load) or write to (store) • Register destination (source) • where in the register file to write to (load) or read from (store) • The memory address is formed by • summing the constant portion of the instruction and the contents of the second register 32

  18. Memory Organization 232 Locations • How wide is the memory • What is each unit • Each unit is a bit • 0, 1 • 8-bits = 1 byte • In MIPS memory is byte addressable • 232 locations of 1 byte • Software likes to operate on “words” • 1 word = 4 bytes = 32 bits • 230 locations of 1 word Memory 8-bit 230Locations Memory 32-bit

  19. MIPS Memory Addressing • The memory address is formed by summing the constant portion of the instruction and the contents of the second (base) register lw $t0, 4($s3) #what? is loaded into $t0 sw $t0, 8($s3) #$t0 is stored where? . . . 0001 in location 16 . . . 0 1 1 0 24 Memory $s3 holds 8 . . . 0 1 0 1 20 . . . 1 1 0 0 16 . . . 0 0 0 1 . . . 0 0 0 1 12 . . . 0001 . . . 0 0 1 0 8 . . . 1 0 0 0 4 . . . 0 1 0 0 0 Data Word Address

  20. Compiling with Loads and Stores • Assume • Variable b is stored in $s2 • Base address of array A is in $s3 • What is the MIPS assembly code for A[8] = A[2] - b . . . . . . A[3] $s3+12 lw $t0, 8($s3) sub $t0, $t0, $s2 sw $t0, 32($s3) A[2] $s3+8 A[1] $s3+4 A[0] $s3

  21. Compiling with a Variable Array Index • Assume • A is an array of 50 elements • Base of A is in register $s4 • Variables b, c, and i are in $s1, $s2, and $s3 • What is the MIPS assembly code for c = A[i] - b add $t1, $s3, $s3 #array index i is in $s3 add $t1, $t1, $t1 #temp reg $t1 holds 4*i add $t1, $t1, $s4 #addr of A[i] lw $t0, 0($t1) sub $s2, $t0, $s1

  22. Assembly Generation: Arithmetic Instructions • Instructions, like registers and words of data, are also 32 bits long • Example: add $t0, $s1, $s2 • registers have numbers $t0=$8, $s1=$17, $s2=$18 • Instruction Format: op rs rt rd shamt funct 000000 10001 10010 01000 00000 100000 What do the field names stand for?

  23. MIPS Instruction Fields R Format op rs rt rd shamt funct = 32 bits 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits • op • rs • rt • rd • shamt • funct opcode indicating operation to be performed address of the first register source operand address of the second register source operand the register destination address shift amount (for shift instructions) function code that selects the specific variant of the operation specified in the opcode field

  24. Assembly Generation: Load Instruction • Consider the load-word and store-word instructions, • What would the regularity principle have us do? • New principle: Good design demands a compromise • Introduce a new type of instruction format • I-type for data transfer instructions • previous format was R-type for register • Example: lw $t0, 24($s2) I Format op rs rt 16 bit number 35 18 8 24 100011 10010 01000 0000000000011000

  25. Assembly Generation: Store Instruction sw $t0, 24($s2) op rs rt 16 bit number 43 18 8 24 101011 10010 01000 0000000000011000 • A 16-bit address means access is limited to memory locations within a region of 213 or 8,192 words (215 or 32,768 bytes) of the address in the base register $s2

  26. Assembling Code • Example: A[8] = A[2] – b lw $t0, 8($s3) #load A[2] into $t0 sub $t0, $t0, $s2 #subtract b from A[2] sw $t0, 32($s3) #store result in A[8] • Assemble the MIPS code for these three instructions lw 35 19 8 8 sub 0 8 18 8 0 34 sw 43 19 8 32

  27. MIPS Data Types Bit: 0, 1 Bit String: sequence of bits of a particular length 4 bits is a nibble 8 bits is a byte 16 bits is a half-word 32 bits is a word 64 bits is a double-word Character: ASCII 7 bit code Integers: Unsigned Integers Signed Integers - 2's complement Floating Point

  28. Decimal, Hexadecimal, and Binary MEMORIZE! 1010 1100 0011 (binary) = 0xAC3 10111 (binary) = 0001 0111 (binary) = 0x17 0x3F9 = 11 1111 1001 (binary) 00 0 000001 1 000102 2 001003 3 001104 4 010005 5 010106 6 011007 7 011108 8 100009 9 100110 A 101011 B 101112 C 110013 D 110114 E 111015 F 1111

  29. Unsigned Binary Representation

  30. Signed Binary Representation : -23 = -(23 - 1) = 1011 and add a 1 1010 complement all the bits 23 - 1 =

  31. Memory Address Location Memory 0xf f f f f f f f lw $t0, 24($s2) 2410 + $s2 = . . . 1001 0100 + . . . 0001 1000 . . . 1010 1100 = 0x120040ac 0x00000002 $s2 0x12004094 0x0000000c Note that the offset can be positive or negative 0x00000008 0x00000004 0x00000000 data word address (hex)

  32. MIPS Instructions, so far

  33. Review: MIPS R3000 ISA Registers R0 - R31 • Instruction Categories • Arithmetic • Load/Store • Jump and Branch • Floating Point • coprocessor • Memory Management • Special PC HI LO • 3 Instruction Formats: all 32 bits wide 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits R Format rs rt OP rd sa funct 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits I Format rs OP rt immediate jump target OP

  34. Review: MIPS Organization so far • Arithmetic instructions – to/from the register file • Load/store instructions - to/from memory Memory Processor 1…1100 Register File read/write addr src1 addr src1 data 5 32 32 230 words src2 addr 32 registers ($zero - $ra) 5 dst addr 5 read data src2 data write data 32 32 32 32 bits write data 0…1100 32 32 0…1000 ALU 32 4 5 6 7 0…0100 32 0 1 2 3 0…0000 32 bits byte address (big Endian) word address (binary)

  35. Review: Naming Convention for Registers 0 $zero constant 0 (Hardware) 1 $at reserved for assembler 2 $v0 expression evaluation & 3 $v1 function results 4 $a0 arguments 5 $a1 6 $a2 7 $a3 8 $t0 temporary: caller saves . . . (callee can clobber) 15 $t7 16 $s0 callee saves . . . (caller can clobber) 23 $s7 24 $t8 temporary (cont’d) 25 $t9 26 $k0 reserved for OS kernel 27 $k1 28 $gp pointer to global area 29 $sp stack pointer 30 $fp frame pointer 31 $ra return address (Hardware)

  36. MIPS Data Types Bit: 0, 1 Bit String: sequence of bits of a particular length 4 bits is a nibble 8 bits is a byte 16 bits is a half-word 32 bits is a word 64 bits is a double-word Character: ASCII 7 bit code Integers: Unsigned Integers Signed Integers - 2's complement Floating Point

  37. Yoda says… • Named must your fear be before banish it you can

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