Three Phase Inverter For the FEC 2005 Induction Motor

# Three Phase Inverter For the FEC 2005 Induction Motor

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## Three Phase Inverter For the FEC 2005 Induction Motor

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1. Three Phase InverterFor the FEC 2005 Induction Motor December 2, 2004 Duke Gray Nathan Brown Quasar Hamirani

2. What is the Future Energy Challenge? • The Future Energy Challenge (FEC) has been organized for participation by student engineering teams around the world. The objective is to introduce engineering design innovations that can demonstrate dramatic reductions in residential electricity consumption from utility sources. The innovations should be low in cost, and should have broad potential for the future.

3. FEC 2005 • The goal of FEC 2005 is to design a motor (with drive) with the following specs: • EFFICIENCY > 70 % (current motors <50%) • SPEED: 150 – 5000 R.P.M. • LOAD: 50 – 500 WATTS (at 1500 R.P.M.) • INPUT: SINGLE PHASED VOLTAGE • OUTPUT: THREE PHASED VOLTAGE • COST < \$40.00 U.S. (in quantity) • MTBF > 10 years

4. Motivation for FEC • American Society uses 3.6 trillion kWh continuously (every second) • Roughly 1 billion motors in use in the U.S. • Motors account for around 64% of total U.S. electrical usage. • Motors of the type we are designing (< 500 W) account for 230 billion kWh and 10 % of the total motor electricity consumption

5. Motivation for FEC • For a 20 % increase in efficiency, this would equal a 28 % decrease in induction motor energy usage. • This equates to a cost savings of: (.28)(230 billion kWh)(\$0.07/kWh) = \$4.5 billion/hr.

6. Motivation for FEC • Costs not only dollars and cents. • For each \$ 1 billion in savings: • 6-10 million tons of coal saved • 15-20 million tons of CO2 not released • Greenhouse effect lessened

7. IMPLEMENTATION

8. Three-Phase Inverter Specifications • Voltage Input: 200 Vdc  5V • Output: Three-Phase 100 Vac (line to line) sine wave • Control: Digital TTL commands at 10kHz • Power Supply: 12V, 5V available

9. “HEX BRIDGE” INVERTER

10. CHALLENGE #1: SWITCHES • TWO TYPES RATED FOR OUR NEEDS: • IGBT (HGTP12N60B3D) • 600 V, 15 A , \$1.70 EACH • POWER LOSS SOMEWHAT LINEAR (I*VSAT) • EQUIVALENT RESISTANCE 0.07 OHMS • MOSFET (FQP17N40) • 400 V, 10 A, \$0.96 EACH • 2ND ORDER POWER LOSS (I2*RDS) • EQUIVALENT RESISTANCE 0.27 OHMS

11. CHALLENGE #1: SWITCHES • MOSFET has smaller loss at 3-5 amp range (where we are operating)

12. CHALLENGE #1: SWITCHES • Pro MOSFET: • Considering cost of IGBT (\$1.70 vs. \$0.96) • Losses of IGBT (higher for 3-5 amp range) • Pro IGBT: • On state resistance lower (0.07 vs. 0.27 Ω) We chose to go with FQP17N40 MOSFETS.

13. GATE DRIVE SELECTION • WHAT IS A GATE DRIVER? • A gate driver “tells” the MOSFETS, (switches) when to open and close. • More advanced models have: • Dead time to prevent signal “shoot through”. • Over current protection (surge protection). • Fault “self clearing” mechanisms. • Enable switches to turn on/shut off drive.

14. GATE DRIVE SELECTION • There are many many many gate driver chips to choose from. • Tradeoff: Cost Vs. Functionality • Wanted high MTBF (mean time before failure) therefore, fewer parts (single chip) • Low cost for required ratings • Little or no “external circuitry”

15. GATE DRIVE SELECTION • SOLUTION: The IR 21362 Gate Drive • All six drivers on one chip (fewer parts, MTBF) • Dead time, fault clearing, enable all there • Required “bootstrap” capacitors to charge low side MOSFETS • Cost: \$4.63 in quantity

16. THE CIRCUIT • After deciding on MOSFETS and the gate drive chip, we needed to determine: • Bootstrap Capacitor size and voltage rating • Resistor size and power rating • Diode voltage rating • Implement fault protection circuitry

17. THE CIRCUIT • Bootstrap capacitors are needed with this gate drive to generate a floating voltage supply above the source of the high-side FETs • Bootstrap Capacitor Size Determined By: Qq=Gate charge of high side FET Icbs(leak)=Bootstrap capacitor leakage current Vf=Forward voltage drop across bootstrap diode f=frequency of operation VLS=Voltage drop across low-side FET Therefore, a common capacitor value of 1 µF (50V rating) was selected • A 1 µF capacitor was also used as a decoupling capacitor across the logic supply voltage to cancel wire inductance of circuit

18. THE CIRCUIT • To provide fault detection, a simple shunt resistor was selected. • Voltage divider resistors apply change in logic voltage to the current trip input when the sensed current is too high. • A potentiometer allows the resistance to be tuned, thus altering the current limit. • An LED was added for visual fault indication.

19. THE CIRCUIT • The current sensing resistor rating was determined by the IR 21362 data sheet. • The gate drive requires the input to fall below 0.46 volts in order to trip the circuit. • Therefore, by V2/R, we have: (0.46)^2/0.05 = 4.232 Watts ~ 5.0 Watts Thus, the current sensing resistor was rated for 5 watts.

20. THE CIRCUIT • Determining resistor values: • All resistors have a power rating based upon power (I2*R) going through them. • For our needs, all resistors (save the current sensing resistor) were rated for ¼ Watt. • Theoretically, our gate resistors would have no current flowing in them (Igate = 0). • The others are connected across 5 and 12 volt inputs respectively, thus very low currents.

21. THE CIRCUIT • Diode voltage rating: • Ratings dependent upon “DC blocking voltage”. • As we are sending 200 Vdc to an output of 140 Vac (RMS), we selected a diode voltage rating of 600 V.

22. THE CIRCUIT • The IR 21362 allows you to “set” your own fault clearing time. This permits you to visually see that there has been a fault, yet allows the system to quickly clear it. • We chose 1.5 seconds as a fault clearing time. Thus, R and C values were: • R = 33kΩ C = 47µF • Thus, RC = 1.551 seconds

23. THE CIRCUIT • A negative voltage spike is seen on the gate drive outputs at the beginning of each switch pulse (exceeding the MOSFET gate ratings) • Gate resistors (24) were selected to decrease the amplitude of this spike while keeping the switching delay reasonable.

24. Power Losses • The power levels in the hex-bridge are much greater than those the gate drive circuitry • Losses in the circuit are primarily due to the MOSFETS • Switching losses • Conduction Losses

25. Power Losses Ton = 656ns, toff = 420ns, fsw = 10kHz Pswtotal = 9.13W Rds = 0.27 Pcond-total = 3.24W >Efficiency  97.5% at full load (ignoring gate drive losses)

26. CIRCUIT SCHEMATIC

27. TESTING PROCEDURES • Gate drive operation tested under no load • Output phases tested individually using 60V power supply and resistive loads • High voltage power supply acquired from Power Applications lab to test with 200V target bus voltage • Three function generators were programmed to provide control signals and test three-phase operation • A commercial induction motor was used to test the inverter real operating conditions • Final performance analysis and fine tuning will take place once the other FEC stages are completed

28. THE PICTURES! • Our original circuit, without “bells and whistles”.

29. THE PICTURES! • Here, hooking up a wimpy 120 volt, 125 ohm load.

30. THE PICTURES! • Now with a more robust 200 Volt, 100 ohm load.

31. THE PICTURES! • The edge of the waveform showing delays and switch “slamming”:

32. THE PICTURES! • A more all encompassing picture of all the equipment and the circuit:

33. THE PICTURES! • Our friend, the 200 volt DC supply:

34. Three Phased Current Output

35. MAKING WAVES • Since we are dependent upon another FEC team in FEC for our control signals, we must “make our own” for testing • Incorporated a MATLAB script with three Agilent 33250A waveform generators • Each generator outputs a 10kHz PWM control signal • Each generator phased 120º apart • Allowed inverter to generate three-phase voltage signals to the motor

36. MAKING WAVES • Agilent 33250A waveform generators

37. MOTOR • Again, since another FEC team is currently in the design phase of the final motor, a similar motor was used. • Used the Dayton 3N843 industrial motor rated for 1725 r.p.m. at 208 volts.

38. MOTOR

39. EFFICIENCY • The results of our efficiency measurements are: • Measured 96.3% in preliminary testing. • Preliminary test used different type of motor at 900 r.p.m.

40. DYMOLA 5 – Circuit Simulation • Modeled circuit in Dymola 5 • Simulated the circuit to ensure correct outputs • Circuit simulation completed successfully and three phase current was outputted • Ensured that the circuit design was good • Output waveform on next slide

41. Three Phase Current from DYMOLA

42. PCB DESIGN • PCB design implemented in Layout Plus • Used original schematic from Orcad • Assigned footprints to all components • Back annotated between Orcad and Layout Plus to get components on the board • Used Auto-Route to make all connections

43. Optimization of PCB • Reduced unnecessary long connections • Changed the width of the wire for high voltage bus to prevent overheating of the copper wires • All standard connections are 12 mils thick • Connections for high voltage traces set to 48 mils • Equation used I = k . ∆T 0.44 . A 0.725

44. ROUTED PCB BOARD

45. MTBF • The MTBF for each component is: • ¼ Watt Resistors: 17,732 years • Current sensing resistor: 13,946 years • Diodes: 1,017 years • Capacitors: 17,732 years • IR 21362 Gate Driver: 327 years • MOSFETS: 111 years • LED: 18,253 years • Total MTBF: 72.85 years

46. COST ANALYSIS(PARTS)

47. COST ANALYSIS(LABOR)

48. SUMMARY • Our team has successfully met our objectives. • Inverter designed with high efficiency (96.3%) • Parts cost around \$15.00 (even less in larger quantities) • MTBF surpasses 10 year mark • PCB board layout ready for manufacturing

49. FUTURE EFFORTS • Next year’s inverter team will have to: • Incorporate PCB into overall package. • Implement thermal design additions. • Fix inevitable bugs associated with fusing the sub-assemblies together. • Determine overall project efficiency. • Have fun accepting first prize in the contest!

50. QUESTIONS?