Reconfigurable acceleration of robust frequency-domain echo cancellation

1. Reconfigurable acceleration of robust frequency-domainecho cancellation C. H. Ho1, K.F.C.Yiu2, J. Huo3, S. Nordholm3 and W. Luk1 • Department of Computing, Imperial College London • Department of Industrial and Manufacturing Systems Engineering, The University of Hong Kong • Western Australian Telecommunications Research Institute, The University of Western Australia

2. Introduction • Echo: affects many communication systems • hands-free telephony • VoIP • Adaptive filters employed to cancel echo • Computationally intensive • involves large number of data

3. Achievements • Novel reconfigurable architecture for two-path frequency-domain echo cancellation • Bit-width optimisations with fixed-point saturation arithmetic • Single core: 12.5 times faster than 3.2GHz Pentium-4 machine

4. x(n) h(n) y(n) v(n) Background: transmitting signals • Given input signal x(n), speech v(n), impulse response h(n), then return signal y(n) is

5. Search for filter coefficients to eliminate the input signals, Echo filtering

6. Delayless sub-band filtering e(n) x(n) y(n) - Weighted Transform A(z) D A(z) D h0(n) h1(n) • downsampling input signals and error signals • compute the coefficient of each sub-band • apply to with weighted transform hM-1(n)

7. Robust two-path adaptive filtering • Two filter coefficient • foreground coefficients • background coefficients • Power level to select the coefficients • high power  foreground coefficients • low power  background coefficients

8. Hardware architecture • Support core operations • signals transform and filtering • Fast Fourier transform • transform the input and error signal to frequency domain with multi sub-band • Complex number multiplication • perform the adaptive filtering • Inverse Fourier transform • transform the filtered signal to time domain

9. Datapath • Hf, Hb: coefficients • buf: interface between core and hosts • X: signals in frequency domain

10. Design optimisation • Optimise number representation • explore quantisation error for different bitwidths • Avoid overflow • fixed-point number format + saturation arithmetic • Compare results • double-precision floating point arithmetic • Use of pre-placed FFT core • increase the throughput of FFT • Multiple instances of adaptive filter in an FPGA • increase the throughput of the overall systems

11. Bitwidth optimisation • Perform filtering • without introduce any near-end signal • expected result • all echo-signal is filtered • Choose the smallest bitwidth • which can perform the filtering effectively

12. Results: fixed point optimisation i = 10f = 10 i = 10f = 14 i = 10f = 18 i = 10f = 54

13. Filter performance mixed signals near-end signals filtered signals using optimised fixed point arithmetic filtered signals using double precision arithmetic

14. FPGA Filter implementations

15. Multiple instances on XC4VSX55

16. Current and future work • Embedded system • Bit-width optimisation • Power and energy consumption • Run-time reconfiguration • Adaptive filtering

17. Summary • Novel reconfigurable architecture for two-path frequency-domain echo cancellation • Bit-width optimisations with fixed-point saturation arithmetic • Single core: 12.5 times faster than 3.2GHz Pentium-4 machine