SIFT UPGRADE
This document outlines the development and challenges of upgrading the SIFT and SVX chip designs used in particle physics experiments. Key focus areas include the integration of FPGAs for emulating SVX II, implementing FLASH ADC converters, and addressing issues like differential non-linearity and component variations. Various chip replacement strategies are evaluated, highlighting potential cost implications and the necessity for rigorous testing. The document emphasizes collaboration with FNAL and cost estimates for development, aiming to deliver a robust solution for upcoming projects.
SIFT UPGRADE
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Presentation Transcript
SIFT UPGRADE Marvin Johnson
Background • SVX 2 readout choice • wanted common readout electronics • Charge signal was roughly comparable to silicon • SVX 3 development precluded new SVX chip • Chip was “free” • SIFT development • UC Davis project • Subcontracted to commercial firm • design is not robust • component variation • external noise on threshold • parasitic C on SIFT output • SVX 2 has problems in MCM package
What’s Changed? • Biggest change is in FPGAs • Emulate SVX II for readout • Buffer 64 or 128 data points • Zero suppress the data on the fly. • Fast and inexpensive FLASH ADC converters • Existence of .25 micron designs at FNAL that can be dropped in to new chip designs
3 options • Direct SIFT replacement • SIFT replacement but include pipeline (18 channel) • Replace entire MCM without using the SVX II chip.
Direct Replace • Requires replacement of SIFT in existing MCM’s • Potentially the lowest cost • may have yield problems • Keeps problems with SVX • Input is always open • differential non linearity • Requires a lot of FNAL manpower • New process that has a great deal of unknown risks
SIFT+Pipeline • Only change is to add the pipeline delay to the SIFT • Allows the SVX to be cleared before charge transfer • Eliminates SVX pickup
NEW MCM • Mux analog out to a flash ADC • 10 bit Flash ADC, 2 channels/chip • 3 micro s total conversion time • allows 94 ns/conversion • Chip control from an FPGA • Make daughter board same footprint as MCM • Power consumption appears similar to current MCM • Solves both CFT and preshower in one board
Details • Pipe line is in 0.25 micron. • convert preamp to 0.25 • should part be made rad hard? • Use gate array to zero suppress and put data into SVX format • how to pack 10 bits into format. • Do we need 2 disc. levels? • If yes, how does it get to virtual SVX. • Do we implement digital controls? • how is down loading done? • How is power handled?
schedule and cost • TSMC submission in November • $175K for 10 wafers (6 guaranteed) • Share submission with BTEV pixel • get enough chips for project (if OK) • ~1000 chips/wafer • Packaging cost is $5/chip $15K • chip testing done at FNAL ~$30K • dual 12 bit ADC and FPGA for $30 • Daughter board+stuffing for $50. • pair of adapter boards cost $75. • Total for 2000 is $160K • Is 2000 enough? • Need 50% contingency at this stage • $307K total without TSMC cost • incremental cost over SIFT only is ~$200K assuming labor at FNAL is free. • Done 1 year after submission • need to cycle all AFE boards
Which Option? • FADC gets rid of DNL and readout problems. • Also reduces risk for changing the SIFT parts on MCM’s • FADC gives clean solution to CFT and Preshower • But, it costs more money. • Both solutions probably take the same time • SIFT replacement is more of an unknown • Need to try SIFT repair on 50 parts ASAP. • Chip designer needs to know what to do by the end of May
