1 / 17

class B, AB and D rf power amplifiers in 0,40 um cmos teChnology

class B, AB and D rf power amplifiers in 0,40 um cmos teChnology. Daniele Agnese MSICT – RF System On Chip 2006/’07. Summary. General idea Technology comparison (CMOS, GaAsFET ) Power amplifiers topology Class B Class AB Class D Project description Simulations/Results Conclusion.

gaston
Télécharger la présentation

class B, AB and D rf power amplifiers in 0,40 um cmos teChnology

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. class B, AB and D rf power amplifiers in 0,40 umcmosteChnology Daniele Agnese MSICT – RF System On Chip 2006/’07

  2. Summary • General idea • Technology comparison (CMOS, GaAsFET) • Power amplifiers topology • Class B • Class AB • Class D • Project description • Simulations/Results • Conclusion

  3. General idea • ADS • Power amplifiers tutorial • Transistor’s model • Circuit adaptation • Simulations change

  4. Technology comparison GaAsFET 0.4 μm CMOS Vth -2.5 V 0.5 V VDS - IDS

  5. Power amplifier - Class B • Circuit Crossover distortion: 50% of cycle conducting

  6. Power amplifier - Class AB • Circuit

  7. Power amplifier - Class D • Circuit

  8. Project description • Power supply • Working point (Bias ports) • Transistor’s parameters • Power input signal • Load adaptation

  9. Simulations/Results • Class B – 1/2 50% T=1/850 MHz = 1,2 ns Linear region: Vds < Vgs - Vth

  10. Simulations/Results • Class B – 2/2 PAE = (Pload – Pin) / Psupply

  11. Simulations/Results • Class AB – 1/2

  12. Simulations/Results • Class AB – 2/2

  13. Simulations/Results • Class D – 1/2

  14. Simulations/Results • Class D – 2/2

  15. Conclusion • Improvements: • Optimize transistors width • Efficiency • Matching network • Reduce current leakage

  16. Any questions? Doubts? or comments?

  17. Thank you a lot for your attention!

More Related