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Overview of Network-on-Chip Architectures for ASIC CMOS Design

This presentation provides an in-depth overview of Network-on-Chip (NoC) architectures, comparing them with traditional bus systems within the context of ASIC CMOS design. It highlights the importance of NoC in modern multi-core systems, outlining key benefits such as scalability, modularity, and reduced power consumption. The presentation discusses various NoC architectures including SPIN, CLICHÉ, and Butterfly Fat Tree, emphasizing their operational efficiencies and suitability for contemporary digital designs. Conclusively, it advocates for the adoption of NoC to overcome challenges posed by global communication in chip design.

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Overview of Network-on-Chip Architectures for ASIC CMOS Design

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  1. Network-on-Chip Physical Properties Pooya Saeedi Presentation for “ASIC CMOS” Course of Professor Fakhraie in second semester, Spring 2006 This is a class presentation. All data are copy righted to respective authors as listed in the references and have been used here for educational purpose only.

  2. Outline • Introduction • NoC Definition • Bus vs. NoC • NoC Architectures • Architectures Comparison • Conclusion

  3. Introduction [1] • Devices are scaling • Smaller transistor feature sizes from generation to generation • Power-delay product benefits from device scaling • But global communication does not scale down • Propagation time on global wires will exceed clock period • Power consumed for driving the wire dominate power consumption of other part of the system

  4. Introduction [1] • More to come about scaling • Estimating delays becomes harder • because wire geometry determined later in design flow • In ultra-deep submicron processes, 80% of the delay of critical path will be due to interconnects [2] • Electrical noise due to crosstalk, delay variations and synchronization failure results in bit upset • Conclusion: Transmission of digital values on wires will be slow, power hungry and unreliable

  5. NoC Definition [2] • NoC allows decoupling processing cores from communication fabric • The need for global synchronization is eliminated • Benefits • Explicit parallelism • Modularity • Minimize the usage of global wires • Power minimization • Scalability [3] • Better performance [3]

  6. NoC Definition IP0 IP1 IP2 IP0 IP1 IP7 IP3 IP4 IP5 IP8 IP2 IP5 IP6 IP7 IP8 IP3 IP4 IP6 Multi-SoC design using ad-hoc methods (headache!) NoC Architecture in Multi-SoC design (making life easier!)

  7. Bus vs. NoC [1] • Bus • Rely on shared channel and arbitration mechanism • Suffers from power and performance scalability • Advantage of low complexity and reduced area and control logic • Bus Examples • AMBA => AMBA-AHB => AMBA-AXI

  8. Bus vs. NoC [1] • Higher speed with higher costs • Crossbar switch • Not Scalable • Highly dependent on design traffic pattern

  9. Bus vs. NoC [1] • NoC • Packet-switched, multihop interconnection network • Cores access to network with PP connections • May under-utilize the link or have local congestion • But irregular topologies have to deal with more complex issues

  10. NoC Architectures • Common Architectures • Scalable, Programmable Interconnect Network (SPIN) • Chip-Level Integration of Communicating Heterogeneous Elements (CLICHÉ) • Folded Torus • OCTAGON • Butterfly Fat Tree (BFT)

  11. SPIN [4] • The size of network grows as (NlogN)/8 • Number of switches converge to 3N/4

  12. CLICHÉ [5] • Each node has a separate switch

  13. OCTAGON [6] • At most two hops between two nodes • Each node can be an OCTAGON itself • Increasing wiring complexity

  14. OCTAGON Wiring [6]

  15. BFT [7] • Each switch has four child port and two parent port • The number of switched will be N/2 for large N

  16. BFT Floor Plan [7]

  17. Architecture Comparisons [2]

  18. Architecture Comparisons [2]

  19. Architecture Comparisons [2]

  20. Architecture Comparison [2]

  21. Architecture Comparison [2]

  22. Architecture Comparison [2]

  23. Architectures Layout [2]

  24. Conclusion • NoC • Offers modular, structural and regular approach for on-chip interconnections • Make delay estimation more accurate • Has less problems than irregular architectures • Has lower interconnect energy dissipation • An appropriate architecture should be selected based on the design specification • This novel architecture is going to replace the ad-hoc design of multi-SoC design

  25. References • [1] L. Benini and D. Bertozzi, “Network-on-chip architectures and design methods”, in Proceedings of IEE Computer Digital Technology, March 2005. • [2] P. P. Pande et al., “Performance Evaluation and Design Trade-Offs for Network-on-Chip Interconnect Architectures, IEEE Transaction on Computers, August 2005. • [3] W. J. Dally and B. Towles, “Route Packets, Not Wires: On-Chip Interconnection Networks”, Design Automation Conference, June 2001. • [4] P. Guerrier and A. Greiner, “A Generic Architecture for On-Chip Packet-Switched Interconnections”, DATE 2000 • [5] S. Kumar et al., “A Network on Chip Architecture and Design Methodology”, ISVLSI, 2002. • [6] F. Karim et al., “An Interconnect Architecture for Networking Systems on Chip”. IEEE Micro Sep-Oct 2002. • [7] P. Pande et al., “Design of a Switch for Network on Chip Applications”, ISCAS 2003.

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