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Understanding Instruction Level Parallelism (ILP) in Computer Architecture

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Instruction Level Parallelism (ILP) is a crucial concept that measures how many instructions can be executed simultaneously within a single clock cycle. This article explores parallel instructions, which are independent and can be executed without waiting on each other. We delve into various levels of parallelism, including bit-level, loop-level, and thread-level parallelism. The piece discusses how compilers can convert sequential code into parallel instructions and the hardware implementations like pipelining and superscalar architecture that enhance ILP, along with techniques for dependency checking, out-of-order execution, and more.

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Understanding Instruction Level Parallelism (ILP) in Computer Architecture

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  1. Instruction Level Parallelism(ILP) Colin Stevens

  2. What is a parallel instruction? • ILP is a measure of the number of instructions that can be performed during a single clock cycle. • Parallel instructions are a set of instructions that do not depend on each other to be executed. • Hierarchy • Bit level Parallelism • 16 bit add on 8 bit processor • Instruction level Parallelism • Loop level Parallelism • for (i=1; i<=1000; i= i+1)  x[i] = x[i] + y[i]; • Thread level Parallelism (SMT, multi-core computers)

  3. Making Computers Think Parallel • Human • Write code yourself, directly controlling each processor • Compiler • Let the compiler convert your sequential code into parallel instructions. • Hardware

  4. Implementations of ILP • Pipelining • Superscalar Architecture • Dependency checking on chip. • Multiple Processing Elements eg. ALU, Shift • VLIW (Very Long Instruction Word Architecture) • Simple hardware, Complex Compiler • Multi processor computers

  5. Pipelining http://en.wikipedia.org/wiki/Image:Fivestagespipeline.png • Superscalar http://en.wikipedia.org/wiki/Image:Superscalarpipeline.png

  6. Hardware Techniques Out of order execution Window Size Speculative execution Branch Prediction Branch Fanout Compiler Techniques Register Renaming ADD $t0,$s1,$2 SW $t0, 0($s3) ADD $t0,s$4,$s5 SW $t0, 0($s6) Unrolling loops Takes advantage of loop level parallelism Identifying parallel instructions

  7. References • http://en.wikipedia.org/wiki/Image:Fivestagespipeline.png • http://en.wikipedia.org/wiki/Image:Superscalarpipeline.png • http://www.cs.iastate.edu/~prabhu/Tutorial/PIPELINE/instrLevParal.html

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