VeLo L1 Read Out

1. VeLoL1 Read Out Guido Haefeli VeLo Comprehensive Review 27/28 January 2003

2. To L1T To DAQ VeLo Read Out System VeLo Read out board DAQ IF Shielding wall L1 Pre Processor L1B Event Sync FEM 1m 40m Analog electrical links ADC VREG TTCrx TTCrx Driver Equaliser CAT6 Measured for 60m Attenuation 10db@40MHz Crosstalk -64db@40MHz I2C ECS TTC TTC Repeater board 15m Crate balcony

3. VeLo ROB board functionality • Reads 64 channels or 2048 detector strips. • Individual clock delay and reference voltage for each channel. • Event synchronization and consistency check based on a FE-chip located on each board. • Individual strip pedestal correction . • L1 buffering during 64ms. • Advanced common mode and zero suppression for the L1 trigger. • Zero suppression for the DAQ. • CC-PC based ECS • TTCrx

4. VeLo digitizer board functional overview Clk To L1T event building network L1 zero suppression, clusterization Delay Vref L1T Cluster Fragment Link ADC ADC Sync Error detection Error Flagged Analog data ADC ADC Throttle L1 Buffer controller DAQ Interface TFC Link TTCrx DAQ Cluster Fragment Link To DAQ L1 Decision FE emulator L1 Buffer Parallel ctrl Ctrl Interface ECS Ethernet I2C JTAG

5. Common mode suppression algorithms Tested by mixing "noise" coming from test beam data and "signal" B  from Monte-Carlo (See LHCb VeLo 2001-043) • LCMS (Linear Common Mode Suppression) • Applied on 1 analog channel (32 detector channels ). 8 bit precision. The LCMS algorithm is now the baseline version for the CM suppression. It has shown very good performances. • Regions (RCMS) • These are the same algorithm as LCMS but the linear correction are applied to 8 or 16 detector channels only. Its performance is of course better for non linear CM noise suppression. • Finite Impulse Response (FIR) filter • Its performance for suppressing non linear noise is by its nature much better than the LCMS type. With a FIR filter algorithm fine tuning can be done in order to suppress non linear CM.

6. Prototyping

7. 2048 word sample buffer 4 analog channels TTCrx module 8-bit ADC @ 40MHz ALTERA FLEX FPGA for simple data processing VME interface for data acquisition and board control RB2

8. RB2 Summary RB2 has been tested in the lab and in testbeams for performance measurements (see LHCb note 2002-033). To improve from RB2: • Improve clock distribution on the board (hardware modification have been implemented on existing RB2s ). • Introduce a clock adjustment for each ADC channel to cope with the delay skew on the cable.

9. ECS L1B and DAQI Connector 4 CH ADC Card DAQ Link FPGA L1 Pre Processor L1 Link FPGA TTCrx L1 Link card FE Emulator Sync FPGA RB3 Readout board

10. RB3 tests

11. Beetle setup

12. R R R R A A A A M M M M Outlook to the final ROB (64 Channel Digitizer Board) • Common project for several sub-detectors in LHCb. • The board can also be used with optical receiver cards. • Specification is in preparation, release February 2003 • Pre-production September 2003 • Testing until April 2004 • Final board production July 2004 CC-PC PP 32 Channel ADC TTCrx Input PP Sync L1T DAQ Link PP 32 Channel ADC Power Input PP