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Space-Time-Energy Trade-offs in Nanoelectronic Memory Devices: A Comprehensive Analysis

This analysis explores the critical trade-offs in the performance of nanoelectronic memory devices, particularly those beyond CMOS technology. It highlights the essential parameters of memory elements, including cell size, retention time, access speed, and operating voltage. The paper examines the interdependencies between these factors, especially in relation to device physics and system-level analysis. The work also discusses the comparison of charge-based memories with non-charge-based options, providing insights into the challenges faced in achieving optimal performance in emerging memory technologies.

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Space-Time-Energy Trade-offs in Nanoelectronic Memory Devices: A Comprehensive Analysis

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  1. Nanoelectronic Memory Devices:Space-Time-Energy Trade-offs Ralph Cavin and Victor Zhirnov Semiconductor Research Corporation

  2. Main Points • Many candidates for beyond-CMOS nano-electronics have been proposed for memory, but no clear successor has been identified. • Methodology for system-level analysis • How is maximum performance related to device physics?  SRC/NSF A*STAR Forum on 2020 Semiconductor Memory Strategies: Processes, Devices, and Architectures, Singapore, October 20-21, 2009 http://grc.src.org/member/event/e003676/e003676_MeetingResults.asp

  3. Space-Time-Energy Metrics • Essential parameters of the memory element are: • cell size/density, • retention time, access time/speed • operating voltage/energy. • None of known memory technologies, perform well across all of these parameters • At the most basic level, for all memory elements, there is interdependence between operational voltage, the speed of operation and the retention time. • Cell dimensions are also part of the trade-off, hence the Space-Time-Energy compromise

  4. Space-Action Principle for Memory The Least Action principle is a fundamental principle in Physics (h) Plank’s constant h=6.62x10-34 Js

  5. Three essential components of a Memory Device: • 1) ‘Storage node’ • physics of memory operation • 2) ‘Sensor’ which reads the state • e.g. transistor • 3) ‘Selector’ which allows a memory cell in an array to be addressed • transistor • diode • All three components impact scaling limits for all memory devices

  6. Three Major Memory State Variables • Electron Charge (‘moving electrons’) • e.g. DRAM, Flash • Electron Spin (‘moving spins’) • (STT-) MRAM • Massive particle(s) (‘moving atoms’) • e.g. ReRAM, PCM, Nanomechanical, etc. Note: Electrical I/O always wanted

  7. DRAM schematic Problem 1: In Si devices Ebmax<Eg=1.1 eV Barrier+Selector Storage: N carriers Only volatile memory possible with FET barrier

  8. Volatile electron-based memory: DRAM Selector dC Eb,C Sensor Eb,tr SA a 25fF Storage Node (a=10 nm, K=100) Nel~105 Vcap=10-15 cm3 Problem 2a: External sensing requires large Nel Problem 2b: Large Nelrequires large size of storage node (capacitor) Problem 2c: Series resistance of the storage capacitor increases with scaling

  9. Charge-based injection “easy” in DRAM: Barrierless transport… Write K=100 a~10 nm (>25fF) Dominates at a<10 nm tw~0.1-1 ns

  10. DRAM summary Ta=1 s Ta=10y Ew~10-14 J Ew~310-14 J a=15 nm a=30 nm Volcap~5105 nm3 Volcap~106 nm3 VolFET=104 nm3 VolFET=105 nm3 EtV~10-9 J-ns-nm3 EtV~10-8 J-ns-nm3 DRAM inherent issues: Selector -Low barrier height-Volatility - Remote sensing – Large size of Storage node Sensor

  11. Flash in the limits of scaling Volstorage=2000nm3 Storage Node Nel~10 Selector ~10 nm Sensor ~6nm Nel~10 ~20nm VolFET~3a3 ~3000nm3

  12. Voltage-Time Dilemma • For an arbitrary electron-charge based memory element, there is interdependence between operational voltage, the speed of operation and the retention time. • Specifically, the nonvolatile electron-based memory, suffers from the “barrier” issue: • High barriers needed for long retention do not allow fast charge injection • It is difficult (impossible?) to match their speed and voltages to logic

  13. Flash Summary E~10-16 J t~1 ms=1000 ns Volstorage=2000nm3 VolFET~3a3 ~3000nm3 EtV~10-9 J-ns-nm3 The minimum space-action metric is approximately the same as for the DRAM

  14. Conclusion on ultimate charge-based memories • All charge-based memories suffer from the “barrier” issue: • High barriers needed for long retention do not allow fast charge injection • It is difficult (impossible?) to match their speed and voltages to logic • Voltage-Time Dilemma Non-charge-based NVMs? The Choice of Information Carrier

  15. Spin torque transfer MRAM (Moving spins): Energy Limit (f0~109-1010 c-1) tstore>10 y the anisotropy constant of a material Eb = KV >~1.4 eV volume D. Weller and A. Moser, “Thermal Effect Limits in Ultrahigh-Density Magnetic Recording”, IEEE Trans. Magn. 36 (1999) 4423

  16. FET selector is biggest component of STT-MRAM in the limits of scaling Eb = KV >1.4eV K~0.1-1 J/cm3 (the anisotropy constant of a material) volume V=1500nm3 Nspin~105 11 nm Storage Node Selecting FET VolFET~3a3 ~3000nm3 J-G. Zhu, Proc. IEEE 96 (2008) 1786

  17. STT-RAM summary VolFET~3a3 ~3000nm3 V=1500nm3 (e.g. 11nm22 nm) Ew~Nspin Eb~105  10-19~10-14 J (Alternative estimate based on optimistic write current/write time projections: Iw~107 A/cm2 and tw~1 ns Ew~107A/cm2 11nm21V 1 ns~10-14 J EtV~10-11-10-10 J-ns-nm3 This looks a little better than the electron-based we looked at earlier!

  18. Scaled ReRAM (courtesy Dr. In YOO/Samsung)

  19. A B Ultimate ReRAM: 1-atom gap ON/OFF~1.61 V=0.5 V Eb=0.38 eV dt=0.075 nm dt<<a

  20. B A Ultimate ReRAM: 2-atom gap ON/OFF~476 V=0.5 V Eb=2.63 eV dt=0.37 nm dt<a

  21. Energy Ultimate Atomic Relay: 4-atom gap Eb (energy barrier for diffusion) 0.5-1 eV

  22. Energy Ultimate Atomic Relay: 4-atom gap Eb (energy barrier for diffusion) 0.5-1 eV (Eb=0.5 eV, n>5)

  23. Ultimate ReRAM: A summary V=1nm3 Nat~100 (64) E~Nat*1eV~10-17J tw~1 ns (can be shown) EtV~10-17 J-ns-nm3 without FET VolFET~3a3 ~3000nm3 EtV~10-14 J-ns-nm3 with FET

  24. Summary Main constraints due to sensor Space-Action, J-ns-nm3 Biggest component Vstor, nm3 tw, ns Ncarriers Ew, J DRAM 105 1 ns Storage Node 105 10-14 ~10-8-10-9 Flash 10 ~10-9 10-16 103 ns 103 Sensor FET Selector STT-RAM 105 103 10-14 1 ns FET ~10-10 ReRAM ~10-14 Selector 1 ns 10-17 1 100 FET Constraints by sensor not considered without FET VolFET~3000nm3 With FET

  25. Summary • Memory cell design is a tradeoff between physical variables needed to achieve long retention times, and short write/read times. • A global metric, space-action, for all memory categories provides insights into most promising extremely-scaled memory devices based on fundamental physics • Scaling Limits of semiconductor component often dominate overall scaling for the memory cell • Our preliminary study suggests a good potential for ReRAM (some constraints are not considered) • Today’s memory technology meets Feynman’s challenge of placing the 24 volumes of Encyclopedia Britannica (~200 MB) on the head of a pin (~.025 cm^2). • Library of Congress (10 Terabytes) on 1 cm^2 by 2020?

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