EE 587SoC Design & Test Partha Pande School of EECS Washington State University firstname.lastname@example.org
Buffered Clock Distribution • Improves precision and Control • Distributed buffers • Amplify clock signals • Isolate local clock nets from upstream load impedance
H-Tree • The primary clock driver is connected to the center of the main “H” structure • The clock signal is transmitted to the four corners of the main “H” • The conductor widths in H-tree structures are designed to progressively decrease as the signals propagate to lower levels of hierarchy. • This strategy minimizes reflections of the high-speed signals at the branching points
Tapered H-Tree • A tapered line, can achieve the same signal characteristics (signal delay and transition time) as the uniform line shown with a smaller total line capacitance. • Tapering a line reduces the coupling capacitance between the signal line and the adjacent ground lines, and, consequently, the total capacitance of the signal line. • Although the line capacitance is reduced, the line resistance is greater, thereby maintaining approximately the same signal characteristics. • A reduction in the line capacitance decreases the dynamic power while an increase in the line resistance decreases the inductive behavior of the interconnect.
Tapered H-Tree (Cont’d) Exponential Uniform
Performance Analysis Uniform Exponential
Clock Power Issues in SoC Design • Different clock rates of the IP blocks
Gated Clock • Cg is the latch’s cumulative gate capacitance connected to the clock. Because the clock switches every cycle, Cg charges and discharges every cycle and consumes significant amount of power. Even if the inputs do not change from one clock to the next, the latch still consumes clock power.
Interfacing Mixed-Timing Domains • Pausible and Stretchable Clocks • Temporarily pause or stretch the receiver’s clock. • Use of Synchronizers • Two-latch synchronizers • Synchronization FIFO • Mixed-clock FIFO
Mixed Timing SoC Asynchronous Synchronous
Clock Distribution of DEC Processor • The single 200 MHz clock signal is distributed through five levels of buffering