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Design and Implementation of VLSI Systems (EN1600) Lecture 13: Logical Effort (2/2)

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Design and Implementation of VLSI Systems (EN1600) Lecture 13: Logical Effort (2/2). Prof. Sherief Reda Division of Engineering, Brown University Spring 2008. [sources: Weste/Addison Wesley – Rabaey/Pearson]. Logical effort generalizes to multistage networks Path Logical Effort

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  1. Design and Implementation of VLSI Systems (EN1600) Lecture 13: Logical Effort (2/2) Prof. Sherief Reda Division of Engineering, Brown University Spring 2008 [sources: Weste/Addison Wesley – Rabaey/Pearson]

  2. Logical effort generalizes to multistage networks Path Logical Effort Path Electrical Effort Path Effort Multistage logic networks Can we write F=GH?

  3. No! Consider paths that branch: G = 1 H = 90 / 5 = 18 GH =18 h1 = (15 +15) / 5 = 6 h2 = 90 / 15 = 6 F = g1g2h1h2 = 36 = 2GH Can we write F = GH? How to fix this problem?

  4. Introduce branching effort Accounts for branching between stages in path Now we compute the path effort F = GBH Branching effort Note:

  5. How large should be each stage in a multi-stage network to achieve the minimium delay? What is the optimal number of stages to achieve the minimum delay Logical Effort can help us answering two key questions

  6. Gate 1 Gate 2 GND Delay is minimized when each stage bears the same effort Answer can be generalized. Thus, for N stages, minimum delay is achieved when each stage bears the same effort 1. What is the optimal size of each stage?

  7. Select gate sizes x and y for least delay from A to B Example: 3-stage path

  8. Logical Effort G = Electrical Effort H = Branching Effort B = Path Effort F = Best Stage Effort Parasitic Delay P = Delay D = Example: 3-stage path

  9. Logical Effort G = (4/3)*(5/3)*(5/3) = 100/27 Electrical Effort H = 45/8 Branching Effort B = 3 * 2 = 6 Path Effort F = GBH = 125 Best Stage Effort Parasitic Delay P = 2 + 3 + 2 = 7 Delay D = 3*5 + 7 = 22 = 4.4 FO4 Example: 3-stage path

  10. Work backward for sizes y = 45 * (5/3) / 5 = 15 x = (15*2) * (5/3) / 5 = 10 Example: 3-stage path

  11. Consider adding inverters to end of path How many give least delay? Define best stage effort 2. What is the optimal number of stages?

  12. has no closed-form solution Neglecting parasitics (pinv = 0), we find r = 2.718 (e) For pinv = 1, solve numerically for r = 3.59 A path achieves least delay by using stages How sensitive is delay to using exactly the best number of stages? ρ = 4 is reasonable Optimal number of stages