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CSE241A VLSI Digital Circuits Winter 2003 Recitation 6: Formal Verification

CSE241A VLSI Digital Circuits Winter 2003 Recitation 6: Formal Verification. Formal Verification - Definition. Formal verification: Logic equivalence checking It verifies the logical equivalence of RTL, gate or transistor level netlists to each other.

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CSE241A VLSI Digital Circuits Winter 2003 Recitation 6: Formal Verification

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  1. CSE241AVLSI Digital CircuitsWinter 2003Recitation 6: Formal Verification

  2. Formal Verification - Definition • Formal verification: • Logic equivalence checking • It verifies the logical equivalence of RTL, gate or transistor level netlists to each other. • Does not guarantee that the initial design met the design specification • Ignores timing information • Only boolean equivalence

  3. Does not test functional correctness No input vector creation necessary No test vectors for logical function Faster verification cycle for the design! Only generates functional vectors for simulation to identify the bugs Formal Verification Advantages

  4. Verifies logic function independent of technology and timing There is no timing check Timing issues must be checked by static timing analysis or dynamic timing simulation. Can compare different technology and different hierarchical structure. Technology Libraries Artisan 0.13 Artisan 0.18 Clock Period = 2.5 ns Clock Period = 5 ns

  5. Formal Verification Application • Verifies equivalence of design at different stages of the ASIC flow • Makes sure that no logical changes are made RTL Logically Equivalent? RTL Modification Synthesized Correctly? Logic Equivalence Checker Synthesized Gate Level netlist CTS, Repeater, P&R, & Optimization correctly? P & R netlist

  6. Formal Verification - Flow • Equivalence checking is a branch of static verification • Employs formal, mathematical techniques • Proves two versions of a design are, or are not, functionally equivalent • EC flow consists of four primary stages: • Read • Match • Verification • Debug • Match and verification stages are those most impacted by design transformations

  7. Read • Read: • 1.During the read stage, both versions of the design are read into the EC tool • 2. Segmented into manageable sections called logic cones • Logic cones (Figure 1) are groups of logic bordered by registers, ports, or black boxes. The output border of a logic cone is referred to as the compare point. Diagram Courtesy of Synopsys

  8. Match • Match: • During the match phase, tools attempt to match, or map, compare points • Reference (golden) design is used for comparison • Types of comparisons: • Non-function (name-based) • Function-based matching methods • Best performance is by the more efficient name-based methods

  9. Compare Points – Logic Cones Diagram Courtesy of Synopsys

  10. Verification Comparison Types • RTL to RTL Verification • Gated clocks addition • Critical path optimization • Other RTL to gate constraints • RTL to Gate Verification • Post synthesis of an HDL design • Gate to Gate Verification • Buffer insertion for re-timing • P&R buffers • Test logic • Clock trees • Scan chains

  11. Formal Proof Issues • Formal tools are great at proving that one logic cone is equivalent to another • Problem: matching up the cones in one input file with the cones in the other input file. • If you can't figure out which cones are supposed to be equivalent, then the tool can't help you • Normally done by matching up the signal names • Done automatically • Some tools alter signal names. • Change the borders of cones • No direct equivalence between cones in one file and the other • Causes formal tool to do tedious process of matching up cones based on the topology of the network • Very time-consuming

  12. Types of Input • Formality, Formal Pro and others use • .db, • Verilog, VHDL • Spice • Edif • Functional descriptions of library cells: • Used for mapping the designs into generic models • RTL and the gate level design netlists: • Are converted into generic models at the mapping stag

  13. Mapping Methods • Name based mapping for design with mostly same names. • No name mapping for designs with mostly different names. • Extra points that exist in one design but not in other are not mapped.

  14. Generic Tool Function - Diagnosis • Locate the error pattern • What is the cause of the mismatch? • List the possible sources of the mismatch • All paths and probable mismatch points • Report gates to trace the fan-in or fan-out of the mismatch points • Check for gated designs

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