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Sub - Nyquist Sampling - System Architecture Characterization presentation

Winter 2010. Performed by Greenberg Oleg Kichin Dima. Sub - Nyquist Sampling - System Architecture Characterization presentation. Supervised by Moshe Mishali Inna Rivkin. General Algorithm Scheme.

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Sub - Nyquist Sampling - System Architecture Characterization presentation

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  1. Winter 2010 Performed by Greenberg Oleg KichinDima Sub -Nyquist Sampling - System ArchitectureCharacterization presentation Supervised by Moshe Mishali Inna Rivkin

  2. General Algorithm Scheme • Expand block: Recieves 4 channels from A/D and expands them to 12 channels 2. CTF block: Discovers supports out of 12 channels 3. DSP & Detector block**: Reconstructs the Initial Signal ** Implemented in the same FPGA

  3. Objective • Designing system architecture • Creating debug environment • Architecture implementation on FPGA

  4. FPGA Environment 1x BOARD: ProcStar||| GiDEL 4x FPGA: Stratix||| EP3SE110 Altera Overview

  5. Single FPGA Overview

  6. Buses on Board • FPGA to FPGA Bits Max.Freq.(MHz) • L/R (I/O) : 100 250 // exp. IC4 • V18_L/R : 10 300 • Main : 40 300 // global • FPGAto PSDB Bits Max.Freq.(MHz) • L/R_IO : 20 300 // 7 to IC1 • L_IN : 8 300 // PSDB to IC • L2_IO : 85 300 // only to IC1

  7. Memories • External from FPGA • Bank A: 256 MB DDR2 DRAM • Bank B,C: 2 x 1 GB SODIMM • Internal inside FPGA • MLAB 640-bit (639 blocks) • Filter delay lines, small FIFO buffers and shift registers • M9K Blocks 9,216-bit (16 blocks) • General purpose memory applications • M114K Blocks 147,456-bit (2150 blocks) • Processor code storage, packet and video frame buffering. • Total Internal Memory: Max.Freq.=333MHz Max.Freq.=166MHz Max.Freq.=500MHz 1MByte

  8. Proposal ArchitectureData Flow DDR DSP (Debug) PciExp. DDR CTF&DSP (Debug) PciExp. 24bit (160MHz) + 1bit Valid FIFO DDR DSP Filter Coefficients Memory (A/D) Matrix Coefficients Matrix Coefficients Expander Expander 1Interface CTF CTF 2Interface 84bit (160MHz)+1bit Valid DSP DSP 3Interface Main Controller 1bit (160MHz) Req_Pulse Interface7 Interface5 6Interface 4Interface 60MHz 48 bit+ valid 24bit (160MHz) + 1bit Valid 1bit (160MHz) Initiate Detector A/D Main Controller Detector 4bit #Iteration Reset 4bit #Iteration Reset Reset Memory (Out) Main Controller Memory_1 (Debug) Memory_2 (Debug)

  9. Proposal ArchitectureMultiple CTF iterations Data Flow DDR DSP (Debug) PciExp. DDR CTF&DSP (Debug) PciExp. 24bit (160MHz) + 1bit Valid+ FIFO DDR DSP Memory (A/D) Expander Interface CTF Interface 88bit (160MHz)+1bit Valid DSP Interface 1bit (160MHz) Req_Pulse Interface Interface Interface Interface 60MHz 48 bit 24bit (160MHz) + 1bit Valid 1bit (160MHz) Initiate A/D Main Controller Detector 4bit #Iteration Reset 4bit #Iteration Reset Reset Memory (Out) Main Controller Memory_1 (Debug) Memory_2 (Debug)

  10. Data Flow Options Expander OR Interface Interface DSP CTF OR

  11. EntitiesAccording the design

  12. EntitiesAccording the design

  13. EntitiesAccording the design

  14. EntitiesAccording the design

  15. Proposal ArchitectureDebug Data Flow 24bit (160MHz) + 1bit Valid FIFO DDR DSP DDR (Debug) Memory (A/D) Exp&CTF model Support Expander DSP Main Controller 1bit (160MHz) Req_Pulse CTF model Valid Initiate 60MHz 48 bit 24bit (160MHz) Detector A/D DDR DSP (Debug) Memory (Out) Memory_1 (Debug)

  16. Proposal Architecture Debug Data Flow 24bit (160MHz) + 1bit Valid+ DDR CTF&DSP (Debug) CTF 88bit (160MHz)+1bit Valid Memory_2 (Debug) Expander Model 1bit (160MHz) Req_Pulse 24bit (160MHz) + 1bit Valid 1bit (160MHz) Initiate 4bit #Iteration

  17. Reserved Signals 10bit (300MHz) Memory_3 DDR (FiFo) Expander CTF DSP Main Controller 10bit (300MHz) 14bit (250MHz) 74bit (250MHz) 10 bit(300MHz) Detector

  18. Protocols • EXPANDER • While(Data) • Valid=1 • Write Data Every Clock • Valid=0 • CTF & DSP & Detector • While(Valid==1) • Read Data Every Clock • EXPANDER (Multiple CTF Cycles) • While(#Iterations!=0) • Wait Until (Req_Pulse=1) • While(Data) • Valid=1 • Write Data Every Clock • Valid=0 • #Iterations-- • CTF (Multiple CTF Cycles) • While(#Iterations!=0) • Req_Pulse=1 • While(Valid) • Read Data Every Clock • Calculate Support • #Iterations--

  19. Protocols • CTF • If (Supports) • Valid=1 • Write #Supports • Write Data • Valid=0 • DSP • If (Valid==1) • Read Data • Read #Support • CTF • If (Initiate_Pulse==1) • Calculate Support • Detector • If(Support Changes) • Initiate_Pulse=1

  20. FIFO & DSP Data FIFO Look_Ahead Support ID Data ID ID FiFo Small Data Out New Support buffer Support buffer Support X Cycles Depth Initiate Detector Expander CTF X Cycles Depth DSP • The small fifo will be implemented in internal FPGA memory • The FIFO will be implemented in external memory

  21. Milestones • Algorithm understanding • Environment learning • Defining System Data Flow • Defining Blocks Interfaces • Defining Blocks Protocols • Architecture Implementation Yes Inprogress Inprogress In progress In progress No

  22. What’s Next? • Architecture: • Receiving final requirements from all groups - 16/12/09 • Creating generic debug environment – 20/12/09 • Ending Interfaces between the components/memories – 27/12/09 • Final recheck of the design/week off – 8/01/10 • Implementation: • Control Units • Interfaces • Memories • Architecture Starting 8/01/10

  23. Questions Thank You For Listening.

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