Sub- Nyquist System Optimization

1. By: Daniel Barsky Natalie Pistunovich Supervisors: Rolf Hilgendorf Inna Rivkin Sub-NyquistSystem Optimization Final Presentation

2. Outline • Previous work • Test environment description • Test results • Conclusions • Future work

3. Previous Work

4. Reminder – Pre-simulation analysis Memory FPGA 1 FPGA 2 FPGA 3 73% 98% 75% Expander CTF DSP Q-Frame . . . OMP A† Controller Support Change Detector

5. Reminder – Pre-simulation analysis (Cont.) • Reconstruction Delay: • Expander - ~15 cycles (@120MHz) • CTF – ~1450 cycles (@120 MHz) • DSP - ~500 cycles (@120 MHz) New Incoming Sample Pseudo-Inverse Delay Q-Frame Delay Sample ready For reconstruction 3.5usec 5usec 11usec Timeline Expander Delay Reconstruction Delay OMP Delay

6. Test Environment

7. Test Environment Overview - Matlab A Matrix Beta Filter Coefficients Beta txt txt General Data A Matrix Filter Coefficients txt txt txt txt

8. Test Environment Overview – Matlab (Cont.) Dataset_1 Dataset_2 Dataset_3 Input Data N N_frame Threshold Support Input Data N N_frame Threshold Support txt txt txt txt txt txt txt txt txt txt

9. Test Environment Overview – Matlab (Cont.) Matlab_pack ...\General Data …\Dataset_1 …\Dataset_2 …\Dataset_3 Matlab_pack VHDL VHDL

10. Test Environment Overview – Modelsim (Cont.) Filter Coefficient FIFO A Matrix β Filter Coefficients Input Samples Expanded Samples Expander Samples FIFO Supply Input Samples N Recalculate Support Delayed Samples CTF SCD DSP N_frame Threshold Support A Matrix Record Reconstructed Data Simulation Controller

11. Filter Coefficients FIFO Module • Reads the filter coefficients from a file • Upon receiving a REQ, outputs a line of 7 coefficients and an ACK signal

12. Test Environment Overview - Modelsim Filter Coefficient FIFO A Matrix β Filter Coefficients Input Samples Expanded Samples Expander Samples FIFO Supply Input Samples N Recalculate Support Delayed Samples CTF SCD DSP N_frame Threshold Support A Matrix Record Reconstructed Data Simulation Controller

13. Supply Samples Module • Reads from the files generated by Matlab: • The input samples • The N, N_frame, Threshold values • The correct support • Upon receiving a positive pulse on the OE signal, starts generating the input samples

14. Supply Samples Module (Cont.) FSM: Opens the first Dataset files (input samples, Nframe , threshold) and waits for an OE command Idle OE Reads samples from the relevant dataset and feeds them to the expander Read next dataset Dataset i<3 done When the dataset samples are done, reads the samples and data for the next dataset Dataset 3 done When all samples are done, do nothing Done

15. Test Environment Overview – Modelsim (Cont.) Filter Coefficient FIFO A Matrix β Filter Coefficients Input Samples Expanded Samples Expander Samples FIFO Supply Input Samples N Recalculate Support Delayed Samples CTF SCD DSP N_frame Threshold Support A Matrix Record Reconstructed Data Simulation Controller

16. A matrix, β coefficient modules • Read the appropriate data from A file • Upon receiving an address, output The appropriate data

17. Test Environment Overview – Modelsim (Cont.) Filter Coefficient FIFO A Matrix β Filter Coefficients Input Samples Expanded Samples Expander Samples FIFO Supply Input Samples N Recalculate Support Delayed Samples CTF SCD DSP N_frame Threshold Support A Matrix Record Reconstructed Data Simulation Controller

18. Samples FIFO module • Upon receiving a WE, stores incoming samples from the expander • Upon receiving OE, outputs stored samples to the DSP for reconstruction • Maximum FIFO length – defined by a Generic • Actual FIFO length – 4294 samples (@20MHz)

19. Test Environment Overview – Modelsim (Cont.) Filter Coefficient FIFO A Matrix β Filter Coefficients Input Samples Expanded Samples Expander Samples FIFO Supply Input Samples N Recalculate Support Delayed Samples CTF SCD DSP N_frame Threshold Support A Matrix Record Reconstructed Data Simulation Controller

20. Simulation Controller • The main part of the testbench • Receives all status signals from all blocks, and sends control signals to all blocks • Consists of 3 FSMs – Expander FSM, CTF FSM, DSP FSM

21. Simulation Controller (Cont.) Expander FSM: Initializes the expander and starts the process of loading the filter coefficients Init Waits until all coefficients have been loaded and the Expander is ready Raises the “Data Valid” signal while supplying zero samples (to generate phase shift) Wait Ready Done Raises the “Data Valid” signal and inputs real samples to the Expander Samples Done Once the samples are finished, pauses the Expander Ready Phase Delay Input Samples Counter

22. Simulation Controller (Cont.) CTF FSM: Initializes the CTF Init Waits until the CTF is ready Initiates the CTF support calculation and waits for a “Support Valid” signal Waits until DSP acknowledges the new support Wait Ready Idle Waits until the SCD indicates a change in the support, upon which time it will initiate a recalculation of the support Support Change DSP Support ACK Ready Support Valid Calculate Support Wait DSP

23. Simulation Controller (Cont.) DSP FSM: DSP is ready and waiting for the CTF to calculate a new support Wait Support DSP is calculating a new Pseudoinverse matrix Support Valid Pseudoinverse calculation done, samples from the Samples FIFO are used for reconstruction Pseudo Inverse Support Change Pseudoinverse Done Reconst-ruction Support Unchanged

24. Simulation Results

25. Expander Initialization

26. Input Samples & Expander Operation

27. CTF Initialization

28. CTF Support Recovery (Incorrect)

29. CTF Support Recovery (Correct)

30. Sample FIFO

31. DSP Pseudoinverse Calculation

32. DSP Support Change Detector

33. DSP Support Change Detector (False Positives)

34. DSP Support Change Detector (False Positives)

35. DSP Support Change Detector (Failure to detect)

36. Reconstruction Example #1 – AM + sine

37. Reconstruction Example #2 – AM + FM

38. Conclusions

39. Hardware Utilization (based on synthesis results of the different groups, includingarcitecture blocks) 21% 58% 73% 33% 98% 78% 15% 40% 75% 98% 8% 31%

40. Reconstruction Latency Expander CTF DSP 15 Cycles 1087 Cycles 29,823 Cycles 248.5usec Timeline Previous Evaluation: New Incoming Sample New Incoming Sample DSP Delay DSP Delay Sample ready For reconstruction Sample ready For reconstruction 5usec 9.06usec 14.5usec Expander Delay Expander Delay Timeline CTF Delay CTF Delay

41. Further Conclusions • Support calculation is unstable, and extremely sensitive to input phase (relative to the NCO’s phase) • SCD is highly prone to misdetections & false positives! • The system seems to have more trouble with FM signals than with AM/sine

42. Future Work

43. Future Work • Characterize the dependency of the support calculation on the input phase • Use fewer resources at a higher clock frequency at the reconstruction stage - in an attempt to squeeze it in with the Expander • Reimplement Pseudoinverse to share resources with the CTF, to fit them both in the same FPGA • Simulate & integrate implementation

44. Gantt Chart