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A System-Level Stochastic Benchmark Circuit Generator for FPGA Architecture Research. Cindy Mark Prof. Steve Wilton University of British Columbia Supported by Altera and NSERC. Introduction: Overview. FPGA architecture studies require benchmark circuits Realistic, big, and varied
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A System-Level Stochastic Benchmark Circuit Generator for FPGA Architecture Research Cindy Mark Prof. Steve Wilton University of British Columbia Supported by Altera and NSERC
Introduction: Overview • FPGA architecture studies require benchmark circuits • Realistic, big, and varied • Current circuits are small • MCNC: 24 LE to 7694 LE • Stratix III: 19,000 LE to 135,200 LE • Alternatives • ASIC: requires conversion • Synthetic: designed for sizes similar to MCNC circuits • Contribution: SOC synthetic circuit generator • Glues modules into realistic, big netlists • Allows customization of the circuit content
Research Approach Survey of Circuit Designs Generator Development
Circuit Characterization: Survey • 66 Block Diagrams • 24 industrial • 42 academic • Applications: • Communication • Multimedia • Processor
Circuit Model • Leaf Modules • Processor • Interface • Controller • Cores • Networks • Bus • Dataflow • Star • Leaf modules connected by networks • Networks are hierarchical, and arranged in a tree
Circuit Characterization: Trends Hierarchy Depth Distribution 1 2 3 4
Circuit Characterization: Trends Network # Distribution on Level 2
Circuit Characterization: Trends Number of Modules per Dataflow Number of Modules per Bus Number of Modules per Star
Circuit Generator: Overview • Constraints file: • # hierarchy levels, # blocks, # networks, bus width • Can specify any combination • One BLIF library directory per module type
Circuit Generation: Example 1 2 3 4
Circuit Generator: Implementation • Modules • MCNC • OpenCores • Synthetic • Networks • Bus: AMBA single master • Dataflow: with feedback • Star: no feedback
Reset Interrupt Circuit Generator: Implementation • Where are the fine grained connections? • Some generated through the network process
Comparison: Overview • Evaluation of SOC circuits as they scale • Comparison to other synthetic generators • GEN: purely combinational • GNL: FFs and IOs • Characteristics • Post-Routing: channel width, wirelength, crit. path
Results: Locality New GNL
Conclusion: Limitations • High number of IO pins • Caused by star networks • Mismatch between bus width and module IO pins • Head and tail of dataflow networks
Conclusion: Ongoing work • Add different block types (memory) • Add different network types • Improve the modeling of reset, interrupt • Improve the modeling of blocks
Conclusion: Status • Can generate circuits 150k LE and up • Works on Linux / Windows • Works better on Linux • Manual • Available for download: • www.ece.ubc.ca/~cindym/
Conclusion: Summary • We have developed a synthetic SOC circuit generator suitable for architectural research • Based on an analysis of published block diagrams • Assumes a tree-like network hierarchy that connects existing BLIF blocks • Resulting circuits, in general, display slower growth in complexity and post-routing characteristics relative to GEN and GNL.
