1 / 28

Fast sampling for Picosecond timing

Fast sampling for Picosecond timing. Jean-François Genat. EFI Chicago, Dec 17-18 th 2007. Outline. Time picking strategies Timing using MCPs Fast Sampling chip Technologies Conclusions. J ean -F rancois Genat, EFI, Dec 17-18 th 2007, Chicago.

Télécharger la présentation

Fast sampling for Picosecond timing

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript


  1. Fast sampling for Picosecond timing Jean-François Genat EFI Chicago, Dec 17-18th 2007

  2. Outline • Time picking strategies • Timing using MCPs • Fast Sampling chip • Technologies • Conclusions Jean-Francois Genat, EFI, Dec 17-18th 2007, Chicago

  3. Time picking techniques • Discriminators can be: • - Single Threshold • Derivative’s Zero-crossing • - Multiple Thresholds • CFDs (many flavours) • All make assumptions on the signal waveform • depending upon detector + front end processing • Fast samplingand digitization • Extract most of the pulse information if sampling is • fast enough to resolve the signal rise-time • Digital processing allows any kind of time (and amplitude) extraction • Time accuracy depends on the sampling rate and amplitude ranges Jean-Francois Genat, EFI, Dec 17-18th 2007, Chicago

  4. 10-100 GHz sampling • Fast sampling: • High rate sampling and pulse reconstruction knowing the waveform allows to get accurately: • - Amplitude • Time • using for instance least squares algorithms (Cleland & Stern) • On-chip digital oscilloscopes, integrated in multi-channel analog memory chips: Labrador (Hawaii), SAM (Saclay) • Digital signal processing can also be integrated Jean-Francois Genat, EFI, Dec 17-18th 2007, Chicago

  5. Outline • Time picking strategies • Timing using MCPs • Fast Sampling chip • Technologies • Conclusions Jean-Francois Genat, EFI, Dec 17-18th 2007, Chicago

  6. MCPs timing performance Jean-Francois Genat, EFI, Dec 17-18th 2007, Chicago

  7. Fast signals 0 1 2 3 4 5 ns Jean-Francois Genat, EFI, Dec 17-18th 2007, Chicago

  8. Fast Sampling with Si detectors Input signal 30ns peaking time (detector + noise) S/N = 30 Peaking time = 50ns Noise spectrum Serial, 1/f Amplitude and time spreads sigma(a) =2%, sigma(t)= 1.2 ns A few nanoseconds measured (M. Friedl, M. Pernicka, Vienna) Jean-Francois Genat, EFI, Dec 17-18th 2007, Chicago

  9. Fast sampling simulations Simulated waveforms: White noise added to randomly delayed pulses Peaking time = 200ps 256 samples S/N=50 Peaking time = 160ps 128 samples S/N=60 2ns 1ns Sigma(time) = 6ps Sigma(time) = 8.3ps Residual (no noise) : 3ps No sensitivity to amplitude distribution Infinite dynamic range assumed Jean-Francois Genat, EFI, Dec 17-18th 2007, Chicago

  10. Outline • Time picking strategies • Timing using MCPs • Fast Sampling chip • Technologies • Conclusions Jean-Francois Genat, EFI, Dec 17-18th 2007, Chicago

  11. Counter and picosecond Vernier timer Triggering discriminators 500 MHz Clock Wilkinson AD Read Cntrl Inputs Analog storage Output Time stamps Write and Read control Figure 1 Fast sampler block diagram 10-100 GHz sampling Jean-Francois Genat, EFI, Dec 17-18th 2007, Chicago

  12. Blocks Capacitor bank (SCA): - number of channels - depth - dynamic range - droop, crosstalk Timing generator - time step - clock frequency - use Vernier to increase sampling frequency Triggering Discriminators - threshold - speed - delay ADC (Wilkinson) - number of channels - number of bits - clock speed Control and processing Overall: - input to SCA bandwidth - temperature sensitivity - calibration - power Jean-Francois Genat, EFI, Dec 17-18th 2007, Chicago

  13. N taps main DLL Clock input th tv M taps Vernier DLLs th = Tclock/N, tv = Tclock/M N and M relatively primes LSB = th-tv N x M delayed outputs Timing generator Increasing delays Use as much as possible clock locked looped delays Routing of delays to SCA critical Jean-Francois Genat, EFI, Dec 17-18th 2007, Chicago

  14. Clock Digital Delay Lines: DLL Delay locked loop: Interpolate delays within a clock period N delay elementst Delays control Time arbiter Clock feeds the digital delay line Phase arbiter locks delays on clock period M. Bazes IBM, Proc. IEEE JSSC 1985 p 75 Jean-Francois Genat, EFI, Dec 17-18th 2007, Chicago

  15. Phase lock Clock DLL output Phase arbiter Delay control Lag Lag Lead OK Jean-Francois Genat, EFI, Dec 17-18th 2007, Chicago

  16. Delay elements Active RC element: R resistance of a switched on transistor C total capacitance at the connecting node Typically RC = 1-100 using current IC technologies N delay elementst sis technology dependent: the fastest, the best ! Within a chip s ~ 1 % a wafer s ~ 5-10% a lot s ~ 10-20% [Mantyniemi et al. IEEE JSSC 28-8 pp 887-894] Jean-Francois Genat, EFI, Dec 17-18th 2007, Chicago

  17. Time controlled delay Vdd Delay control thru Vdd Delay controls thru gates voltages PMOS PMOS B=A NMOS NMOS Spread=12 ps Propagation delay t ~ 10-100 ps CMOS Technology 90nm: t ~ 20-40 ps 65nm in production today 100ps TDC 0.6mm CMOS (1992) Jean-Francois Genat, EFI, Dec 17-18th 2007, Chicago

  18. write read reset Switched Capacitors Array Flavours: - Sampling Cap switched in the loop of an opamp - Differential implementation Jean-Francois Genat, EFI, Dec 17-18th 2007, Chicago

  19. Discriminators Do not need the ps accuracy (reference is the main clock) Stops the sampling after a (programmable) delay Jean-Francois Genat, EFI, Dec 17-18th 2007, Chicago

  20. ADC Wilkinson preferred in terms of power and Silicon area since heavily parallel See Eric Delagnes slide: Fast Wilkinson: Clock interpolated using a DLL 100 ps counter 10 times faster Same 12 bit accuracy Jean-Francois Genat, EFI, Dec 17-18th 2007, Chicago

  21. ILC 130nm Silicon strips chip Channel n+1 Sparsifier Can be used for fast decision S aiVi > th (includes auto-zero) Time tag Single ramp 10 bits ADC Channel n-1 reset reset Analog samplers Strip Ch # Preamp + Shapers Waveforms Counter CMOS 130nm ADC Clock 3-96 MHz Jean-Francois Genat, EFI, Dec 17-18th 2007, Chicago

  22. Outline • Time picking strategies • Timing using MCPs • Fast Sampling chip • Technologies • Conclusions Jean-Francois Genat, EFI, Dec 17-18th 2007, Chicago

  23. Technologies SiGe - Not many benefits compared to Deep Sub-Micron CMOS - In addition CMOS from BiCMOS not as fast as pure DSM CMOS 2006 Jean-Francois Genat, EFI, Dec 17-18th 2007, Chicago

  24. CMOS Present designs in CMOS: CERN HPTDC IBM .25 mm 25ps timing generator development .13 mm 6ps timing generator Hawaii BLAB 1 TSMC .25 mm 6 GHz 10b sampling dev 2 TSMC .25 mm 10 GHz Saclay SAM AMS .35 mm 2 GHz 12b sampling 90nm CMOS available from MOSIS, Europractice Drawbacks - Reduced voltage supply - Leaks Jean-Francois Genat, EFI, Dec 17-18th 2007, Chicago

  25. Outline • Time picking strategies • Timing using MCPs • Fast Sampling chip • Technologies • Conclusions Jean-Francois Genat, EFI, Dec 17-18th 2007, Chicago

  26. Backup J-F Genat, RP220/420 Paris Workshop, Sept 12th 2007

  27. Multi-threshold performance Multi-threshold: sampling times instead of amplitudes : - Number of thresholds 4-8 - Thresholds values equally spaced - Order of the fit: 2d order optimum Extrapolated time

  28. MCP PMT single photon signals Actual MCPs signals K. Inami Univ. Nagoya Tr = 500ps tts= 30ps MCPs segmented anode signals simulation 20 photoelectrons tts = 860 fs H. Frisch, Univ. Chicago + Argonne BUT N photo-electrons improves as Jean-Francois Genat, EFI, Dec 17-18th 2007, Chicago

More Related