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Timing System Developments

Micro-Research Finland Oy. Timing System Developments. Jukka Pietarinen EPICS Collaboration Meeting Shanghai March 2008. Micro-Research Finland Oy. Register Map Changes (new register mapping). Now available for CompactPCI boards PMC-EVR Main features

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Timing System Developments

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  1. Micro-Research Finland Oy Timing System Developments Jukka Pietarinen EPICS Collaboration Meeting Shanghai March 2008

  2. Micro-Research Finland Oy Register Map Changes (new register mapping) • Now available for • CompactPCI boards • PMC-EVR • Main features • Direct addressing of registers, sequencer memories, etc. • Register space has grown to 64 kbytes • One type of EVR pulse generator • 128 bit wide EVR event mapping RAM: • No overlapping mapping bits • Mapping registers for HW inputs and outputs • EVG interrupt support • EVR Upstream signaling • Will be available for VME versions later 12.3.2008 jukka.pietarinen@mrf.fi

  3. Micro-Research Finland Oy EVR Pulse Generator • One type of EVR pulse generator: • Registers for delay, width, prescaler with SW probable width • No more different types of outputs: PDP, OTP, TEV, LVL 12.3.2008 jukka.pietarinen@mrf.fi

  4. Micro-Research Finland Oy Event Mapping RAM 12.3.2008 jukka.pietarinen@mrf.fi

  5. Micro-Research Finland Oy Register Map Changes • Same set of VHDL sources for all form factors • EVR configuration determined by a VHDL package • Number of front panel I/O • Number of Universal I/O modules • Backplane I/O • Number of pulse generators (max. 32) • Pulse delay and width extents 12.3.2008 jukka.pietarinen@mrf.fi

  6. Micro-Research Finland Oy VHDL package for cPCI-EVR -- Event Receiver configuration parameters -- C_EVR_PULSE_GENS sets the number of internal pulse generators constant C_EVR_PULSE_GENS : integer := 10; constant C_EVR_TTL_INPUTS : integer := 2; -- C_EVR_TTL_OUTPUTS defines the number of front panel TTL outputs constant C_EVR_TTL_OUTPUTS : integer := 0; -- C_EVR_CML_OUTPUTS defines the number of front panel CML outputs -- note: the CML output mapping registers are appended after the -- TTL output mapping registers constant C_EVR_CML_OUTPUTS : integer := 0; -- C_EVR_UNIV_OUTPUTS defines the number of Universal outputs -- = twice the number of Universal I/O slots constant C_EVR_UNIV_OUTPUTS : integer := 10; constant C_EVR_UNIV_INPUTS : integer := 10; -- C_EVR_GPIOS defines the number of GP I/Os in Universal I/O slots constant C_EVR_GPIOS : integer := 8; -- C_EVR_TB_OUTPUTS defines the number of Transition Board/Rear I/O/ -- PXI star trigger/trigger bus outputs constant C_EVR_TB_OUTPUTS : integer := 0; 12.3.2008 jukka.pietarinen@mrf.fi

  7. Micro-Research Finland Oy VHDL package for cPCI-EVR (cont.) -- C_EVR_PRESCALERS defines the number of prescalers constant C_EVR_PRESCALERS : integer := 3; constant C_EVR_PULSE_PRESC_RANGE : integer_array(0 to C_EVR_PULSE_GENS-1) := (16, 16, 16, 16, 0, 0, 0, 0, 0, 0); constant C_EVR_PULSE_DELAY_RANGE : integer_array(0 to C_EVR_PULSE_GENS-1) := (32, 32, 32, 32, 32, 32, 32, 32, 32, 32); constant C_EVR_PULSE_WIDTH_RANGE : integer_array(0 to C_EVR_PULSE_GENS-1) := (32, 32, 32, 32, 16, 16, 16, 16, 16, 16); constant C_EVR_PRESC_RANGE : integer_array(0 to C_EVR_PRESCALERS-1) := (16, 16, 16); constant C_EVR_MICREL_WORD : std_logic_vector := X"0C928166"; constant C_EVR_USEC_DIVIDER : std_logic_vector := X"007D"; constant C_EVR_USE_TRANSMITTER : boolean := TRUE; -- C_EVR_ENABLE_BACKWARD_CHANNEL enables EVR event transmission and -- disables loopback of received event stream constant C_EVR_ENABLE_BACKWARD_CHANNEL : boolean := TRUE; 12.3.2008 jukka.pietarinen@mrf.fi

  8. Micro-Research Finland Oy Downstream Timing Hardware Triggers/Clocks RF input (50 MHz to 1.6 GHz) Rep. Rate Trigger Input e.g. 50 Hz TTL Event Generator (EVG) Multimode fiber 12-Way Fan-Out 12-Way Fan-Out Event Receiver (EVR) Event Receiver (EVR) Event Receiver (EVR) Hardware Outputs 12.3.2008 jukka.pietarinen@mrf.fi

  9. Micro-Research Finland Oy Timing System with Upstream Hardware Triggers/Clocks RF input (50 MHz to 1.6 GHz) Rep. Rate Trigger Input e.g. 50 Hz TTL Event Generator (EVG) Multimode fibers Fan-Out/Concentrator Fan-Out/Concentrator Event Receiver (EVR) Event Receiver (EVR) Event Receiver (EVR) Hardware Outputs 12.3.2008 jukka.pietarinen@mrf.fi

  10. Micro-Research Finland Oy Timing System Upstream Channel • Backward events • EVR send events on external HW triggers • Forwarding of received events filtered by event code • Concentrators forward events on first in first out basis • Backward Distributed Bus • External inputs provide signals to up to eight backward distributed bus signals • Concentrators combine distributed buses from all EVRs (bitwise OR) • Backward Data Transmission • Data buffers of up to 2k may be send upstream • Concentrators pass data on as-is, if EVR identification is needed and ID has to be included in data • Note: concentrator buffering capacity is limited • Fiber delay measurement 12.3.2008 jukka.pietarinen@mrf.fi

  11. Micro-Research Finland Oy Fan-Out Concentrator Module (cPCI-FOUT-CT-8) 12.3.2008 jukka.pietarinen@mrf.fi

  12. Micro-Research Finland Oy Fiber Delay Measurement Setup EVG FOUT- CT-8 Fiber under test EVR Loopback EVR Loopback EVR Scope 12.3.2008 jukka.pietarinen@mrf.fi

  13. Micro-Research Finland Oy Fiber Delay Measurement Heater 80˚C std.dev. between 10:40 and 10:55 2.2 ps Heater 70˚C Scope off Heater 50˚C 12.3.2008 jukka.pietarinen@mrf.fi

  14. Micro-Research Finland Oy Fiber Delay Measurement Cold Spray 12.3.2008 jukka.pietarinen@mrf.fi

  15. Micro-Research Finland Oy Form Factors • Event Generator • VME64x • PXI/CompactPCI • Event Receiver • VME64x • PMC • PXI/CompactPCI 3U • Future form factors: • CompactPCI 6U? • CompactRIO (National Instruments)? • EPIC form factor? (see http://www.pc104.org) • Integrated CPU (either soft-CPU inside FPGA or Freescale Coldfire) • Integrated EVR • PC104 bus / PCI bus • uTCA? 12.3.2008 jukka.pietarinen@mrf.fi

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