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Low-Cost Irrigation Management: Transistor-Level Schematics & Floor Plans Presentation

This presentation outlines the development process for the SprinklerBuddy low-cost irrigation management system. It details the project status, specifications, and architectural designs, including refined floor plans and transistor-level schematics. The project features a total of 30,397 transistors with a design area of 178 mm². The presentation also discusses design challenges, including control logic issues and optimization strategies for reducing transistors. Future goals involve perfecting control logic, optimizing gates, and progressing to layout design.

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Low-Cost Irrigation Management: Transistor-Level Schematics & Floor Plans Presentation

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Presentation Transcript

  1. SprinklerBuddy “Low Cost Irrigation Management For Everyone ! ” Presentation #5: “Transistor Level Schematics and Another Floor Plan” 2/21/2007 Team M3 Sasidhar Uppuluri Kalyan Kommineni Kartik Murthy Panchalam Ramanujan Design Manager: Bowei Gai

  2. CurrentStatus • Determine Project  • Develop Project Specifications  • Plan Architectural Design  • Determination of all components in design  • Detailed logical flowchart  • Design a Floor Plan (refined again) • Create Structural Verilog  • Make Transistor Level Schematic  (some control issues) • Layout  • Testing (Extraction, LVS, and Analog Sim.) 

  3. Old (Naïve) Floor Plan Floor Plan

  4. Somewhat Better FloorPlan

  5. Last Week’s FloorPlan

  6. This Week’s First Try

  7. Current Floor Plan

  8. Individual Modules:

  9. Transistor Count … Total = 30,397

  10. New Design Size • 457um x 391 um • ~ 1 : 1.16 aspect ratio • .178 mm^2 area • .168 Transistor Density

  11. Schematics: SRAM

  12. Schematics: Flip Flops

  13. Schematics: Read & Write to SRAM Read Write

  14. Schematics: ROMs

  15. Schematics: FP Units Multiplier Adder

  16. Schematics: Control FP Adder Hourly Update

  17. Design Challenges and Implementation DecisionsFor The Past Week

  18. Problems/Questions • Small Problems with Control Logic in Schematic • Can we reduce more transistors with better logic ? • Any way to move the SRAM from the middle of our chip?

  19. For Next Week • Perfect our Control Logic in the Schematic • Continue to reduce and optimize gates • Start Layout !

  20. Some Other Slides For Reference…

  21. Block Size Estimates

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