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Post Programming Burn-in of Actel 0.25µm FPGA’s MAPLD 2002

Post Programming Burn-in of Actel 0.25µm FPGA’s MAPLD 2002

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Post Programming Burn-in of Actel 0.25µm FPGA’s MAPLD 2002

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  1. Post Programming Burn-in of Actel 0.25µm FPGA’sMAPLD 2002 Minal Sawant, Dan Elftmann, Werner van den Abeelen, John McCollum, Solomon Wolday and Jonathan Alexander Actel Corporation Sunnyvale

  2. Outline • Devices • RT54SX-S • A54SX-A • Test Modes for blank devices • Blank Burn-in • Dynamic • Static • Programming and Testing • Dynamic Post Programming Burn-in (DPPBI) • HTOL (High Temperature Operating Life) • LTOL (Low Temperature Operating Life) • Improper Burn-in • Conclusion

  3. Devices • RT54SX-S and A54SX-A : • Both use the same 0.25µm process technology • RT54SX32S and A54SX32A family use 3 metal layers while the RT54SX72S and A54SX72A devices are implemented using 4 metal layers • RTSX-S utilizes TMR technique on R-cells for SEU mitigation • Three flip-flops are implemented using a majority gate voting circuit • Self-refreshing TMR built into every register • Built in feature thereby eliminating need for software techniques • Both families utilize the same antifuse design and process • Comparison of the two families can be summarized as follows:

  4. Unique architecture of the FPGA allows testability via the JTAG interface All routing tracks can be addressed, driven, sampled and read back Sample of the different test modes are listed here: All tracks Ensures no continuity, shorts or leakage issues All logic modules All clocks tested for functionality All I/O buffers All Input modes are configured and tested All programming circuits All un-programmed antifuses Stressed to screen out weak antifuses Ensures highly reliable antifuses Done 100% on every wafer lot Test Modes for blank devices

  5. Sample of the different test modes (continued): “BINNING CIRCUIT” dedicated column Sample of the antifuses are programmed by the Sculptor programmer Ensures functionality of programming circuitry Ensures properly programmed antifuses Gives a measure of speed performance Charge pump Ensures charge pump functionality after power up Standby current measurements are done for all power supplies 100 % of the devices are tested Testing is done at all three Military temperatures of 25°C, -55°C and 125°C Test Modes for blank devices

  6. Actel gate oxide failures are rare: Due to sufficient screening of devices when in the un-programmed state Devices are voltage stressed at test, which is more effective than temperature stress Defect related early failures are also rare MIL-STD-883E requires burn-ins Two types of blank device burn-ins are performed by Actel Dynamic Blank Burn-in (DBBI) Static Blank Burn-in (SBBI) Blank Burn-in

  7. Purpose of DBBI Stress un-programmed antifuses Vertical and horizontal tracks are driven to 0 and 1 alternately Stress inputs, outputs and internal circuits Alternate toggling of tracks also causes input and output tracks of logic modules to toggle Exercises transistors in logic modules Stress I/O’s Toggled via BSR by loading 0,1 and Z patterns as shown below 25% of I/O’s toggle per cycle Dynamic Blank Burn-In (DBBI)

  8. Conditions used for DBBI HCLK, CLKA, CLKB, QCLKA-D (for A54SX72A and RT54SX72S) are driven with 500Khz, 50% duty cycle Vcci =5.5V Vcca = 2.75V Temperature = 125°C Done for 240 (E-flow) /160 (B-flow) hours 100 % of all logic modules, routing tracks and antifuses are stressed at DBBI continuously DBBI is performed for both B, E Military flows DBBI

  9. SBBI is performed for E-flow devices only This burn-in does not toggle any I/O’s or internal nodes Purpose of SBBI Effective screen for mobile ionic contamination failure modes But design of seal ring barriers and improved passivation makes this failure mode highly unlikely Conditions for Burn-in Vcci =5.5V Vcca = 2.75V Temperature = 125°C Static voltage levels on all I/Os and clocks Done for 144 hours Static Blank Burn-In (SBBI)

  10. PROM One transistor per switch element (antifuse) hence die size gets affected Due to minimum programming transistor size, programming currents are limited By operating in the low programming current region, the antifuse link is more susceptible to mechanical stress at temperature This can result in links opening up during bake Actel FPGA One transistor per metal track is required which may have up to 1000 antifuses The larger programming transistors provide higher currents Result: larger, stronger and lower resistance programmed antifuse RESULT: high temperature bakes have no effect on the integrity of the Actel FPGA antifuse PROM versus FPGA

  11. PROM Vs Actel FPGA Programming and Testing

  12. Programming of Actel Antifuse Antifuse to be programmed is addressed and pulses are applied Checks at lower voltages are done to ensure low resistance link has been established Many additional checks are done as listed below: Verifies that only correct antifuses are programmed Verifies each column and channel to ensure correct nets have been generated Pre and Post Icc measurements are performed Checks for any sneak paths End of channel (EOC) tests are performed to check for any track shorts within each channel End of programming (EOP) tests are performed to check for Vcc to GND shorts, column to column shorts, clock to clock shorts, etc All these tests ensure all nets are 100% tested for shorts and continuity A sample of units from every lot are programmed by Actel and tested for functionality prior to blank device shipments No functional failures have been reported by Actel Programming and Testing

  13. Purpose: To address post programming reliability concerns of customers Actel guarantees 100% functionality of the device post programming To prove that customers need not perform PPBI the following testing and reliability data has been collected Actel performs many reliability tests on programmed units Sample of units are programmed to a Quality Control Monitor (QCM) design Design has > 95% utilization of logic modules All user I/O’s are exercised 25% at a time All Global low skew clock networks are utilized Design has self-test blocks to manage power consumption, and maximize all features of the product Devices are tested pre and post burn-in for functionality and DC parametric to check for drifts Dynamic Post Programmed Burn-In (DPPBI)

  14. Two types of burn-ins are performed HTOL To check for CMOS related failures Done at high temperature of 150°C (accelerated) Done for different time periods ranging from 168 to 2000 hours DPPBI HTOL

  15. Two types of burn-ins are performed LTOL To screen for hot electron effects To check for antifuse integrity, since transistor drive currents increase by 20% at low temperatures Done at low temperature of -55°C, since programmed antifuses are more sensitive to current stress Done for different time periods ranging from 168 to 2000 hours DPPBI LTOL

  16. HTOL Data shows 632,000 hours of burn-in and 2 failures. 1st failure was isolated to EOS condition causing transistor to be damaged 2nd failure work is in progress LTOL data shows 354,000 hours of burn-in and NO antifuse failures All data collected for the 0.25µm technology product shows no failures related to antifuses This shows the Actel antifuse to be robust in nature and thus requires no post programming burn-in of devices. But there are other reasons to not perform PPBI… DPPBI Summary

  17. Incorrect burn-in can cause huge problems !!!! It is very important to understand the reasons for performing burn-in under correct conditions What are these incorrect burn-in conditions? Incorrect testing or vectors Incorrect biasing conditions Improper systems Burn-in Board designs, driver boards Over voltage protection circuits, bypass capacitors, driver boards Power supplies, cable lengths, sockets, fans, heaters, ovens Incorrect design of any one of these conditions can result in burn-in failures CMOS Antifuse Improper Burn-in

  18. Spike on Vcca and Vcci at burn-in when heater turns ON Voltage Supply Spikes

  19. Damage to antifuse due to spike on VccA during burn-in Supply Voltage Spike Antifuse damage

  20. Damage to input pin due to EOS during burn-in Input pin Electrical Overstress (EOS)

  21. Actel has observed failures due to improper burn-in conditions during development of acceptable burn-in criteria Spikes on power supply lines Sequence of turning ON/OFF of fans, heaters, ovens etc Lack of bypass capacitors (for low and high frequency) Incorrect voltage settings EOS on input pins Unbiased input pins Thus it is very important to pay detailed attention while designing burn-in systems Customers have reported failures which have been traced to one or more of the above mentioned conditions As we migrate to smaller process technologies and lower power supplies, sensitivity to out of specification transients increases 2.5V spike (for a 5V part) = 50% overstress 2.5V spike (for a 2.5V part) = 100% overstress 2.5V spike (for a 1.5V part) = 167% overstress !!! Improper Burn-in Summary

  22. Unique architecture of Actel FPGA allows testing of blank devices with 100% test coverage Blank burn-ins are performed at Actel Burn-in stresses un-programmed antifuses, logic modules, routing tracks and I/O’s Done on 100 % of the devices Many verifications are performed during programming which ensures a robust link has been established and no unwanted antifuses are programmed Programmed Burn-in at Actel shows highly reliable devices 632,000 hours of burn-in at HTOL 354,000 hours of burn-in at LTOL NO antifuse related failures have been reported! Improper burn-in can result in CMOS or antifuse related failures! Based on the data collected, it is Actel’s position that customers should not perform their own DPPBI Considering the complexities and cost of these devices, burn-in is best left to the vendor! Conclusion