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Hardware Based Floating Point Processing

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Hardware Based Floating Point Processing. All the ingredients for FPGA based floating point 28 nm Variable Precision DSP Block 28nm silicon enhancements for floating point IP: Fused Datapath : efficient floating point in Altera FPGAs Tools: DSP Builder Advanced Blockset

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Hardware Based Floating Point Processing

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  1. Hardware Based Floating Point Processing • All the ingredients for FPGA based floating point • 28 nm Variable Precision DSP Block • 28nm silicon enhancements for floating point • IP: Fused Datapath: efficient floating point in Altera FPGAs • Tools: DSP Builder Advanced Blockset • Matlab/Simulink native support is floating point • Cholesky decomposition / matrix inversion design • Programmable in both matrix size and vector size • Ex: 20x20 with vector size of 10, 240x240 with vector size of 60 • Up to 1 Million matrices per second in a single core for time interleaved 20x20 matrices, multiple cores possible in single device • Floating point roadmap • Silicon / Tools / IP

  2. Single Channel Results: Single Core

  3. Multi-channel Results: Single Core

  4. Cholesky Throughput per FPGA device

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