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Unit 3.5 Adder & Comparator

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Unit 3.5 Adder & Comparator. Combinational Logic Circuits. Combinational logic circuits are circuits such that their output at any instant depends only on the combination of the inputs at that instant, and do not depend on their history.

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Unit 3.5 Adder & Comparator
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  1. Unit 3.5 Adder & Comparator

  2. Combinational Logic Circuits Combinational logic circuits are circuits such that their output at any instant depends only on the combination of the inputs at that instant, and do not depend on their history. So a combinational circuit performs a processing that can be fully specified by a Boolean function. Arithmetic Circuits These are combinational circuits that are used to perform arithmetic operations such as addition, subtraction, multiplication and division.

  3. Half adders Binary addition of two binary digits Let A and B be two binary digits, the following table shows the results of adding them together, where S represents the sum bit and C the carry bit. From the truth table, or using Karnaugh map, we obtian

  4. Half adders Combinational logic implementation Using AND, OR and NOT gates, the half adder is implemented as the following circuit. Using XOR gate, we have Using a block diagram, we have

  5. Full adders The full adders is a combinational logic circuits that implement the addition of three binary digits. Usually one of the input binary digit is a carry from a previous addition. Binary addition of three digits Let the three binary digits be A, B and C. The following truth table details the addition, with S being the sum bit and Co the carry bit.

  6. Full adders We construct the Karnaugh maps for S and Co, as shown below: So Note:

  7. Full adders Combinational logic implementation Using AND, OR and NOT gates, the full adder is given below:

  8. Full adders Using XOR gates for the full adder, we have Or, using half adders, The block diagram representation is

  9. Serial and parallel adders For two binary numbers of n bits, the addition starts at the LSB (Least Significant Bit, i.e. the right most bit) of the two binary numbers. Its sum bit is the LSB of the result and its carry bit is fed into the next significant bits on the left for addition. The process repeats until the MSB (Most Significant Bit, i.e. the left most bit) of the numbers are added.

  10. Serial and parallel adders Serial adder It uses one FA (full adder) with an initial carry of 0 for the LSB, and a memory element to hold the intermediate carries. At each stage, the carry is fed back into the adder together with the next bits from the numbers, until the MSB bits are done. This is illustrated below with a 4 bit serial adder. The serial adder is slow as it has to do the additions n times in sequence, even ignoring the delay in feedback of the intermediate carry.

  11. Serial and parallel adders Parallel adder It uses n FA (full adder) with an initial carry of 0 for the LSB. All bits of the binary numbers are applied simultaneously. The output carry from one FA is connected to the input carry of the FA on the left. This is illustrated below with a 4 bit parallel adder. The parallel adder is much faster than the serial adder.

  12. Serial and parallel adders Propagation delay Although the parallel adder claimed to do the additions for all bits simultaneously, its speed of operations is limited by the carry propagation delay through all stages. The final result is only available when the carry has propagated through all the stages from LSB to MSB, i.e. ripple from LSB to MSB. To eliminate such ripple carry delay, one method is to use look-ahead carry generator circuits.

  13. Comparators A comparator is a combinational logic circuit designed to compare the magnitude of two binary numbers A and B. The results are specified by 3 binary output: A > B, which is 1 if true, 0 otherwise; A = B, which is 1 if true, 0 otherwise; and A < B, which is 1 if true, 0 otherwise. Single-bit comparator The combinational block diagram for a single-bit comparator is

  14. Comparators Let the 3 outputs be Y1 (A>B), Y2 (A=B) and Y3 (A<B). The truth tables for the single-bit comparator is From the truth table, Combinational logic circuit implementation Using XOR gate, the logic circuit is

  15. 2-bit Comparators Consider two 2-bit binary numbers A=A1A0, and B=B1B0. Output Y2 (A=B): Y2 is 1 when both A0=B0 and A1=B1, so Output Y1 (A>B): Y1 is 1 when A1>B1 ; or A1=B1 and A0>B0; so Output Y3 (A<B): Y3 is 1 when A1<B1; or A1=B1and A0<B0; so

  16. 2-bit Comparators Combinational logic circuit implementation Using XOR and other gates, the 2-bit comparator can be implemented as

  17. n-bit Comparators We can generalize the above discussion of 2-bit comparator to n-bit comparator. Apart from the complexity, there is no new concept involved.