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CPUs

CPUs. Caches. Memory management. Cache operation. Many main memory locations are mapped onto one cache entry. May have caches for: instructions; data; data + instructions ( unified ). Memory access time is no longer deterministic. address. data. cache. main memory. CPU. cache

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CPUs

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  1. CPUs • Caches. • Memory management. Principles of Embedded Computing System Design

  2. Cache operation • Many main memory locations are mapped onto one cache entry. • May have caches for: • instructions; • data; • data + instructions (unified). • Memory access time is no longer deterministic. Principles of Embedded Computing System Design

  3. address data cache main memory CPU cache controller address data data Logical address Memory mapping Physical address Caches and CPUs (P.84) Principles of Embedded Computing System Design

  4. Terms • Cache hit: required location is in cache. • Cache miss: required location is not in cache. • Working set: set of locations used by program in a time interval. Principles of Embedded Computing System Design

  5. Types of misses • Compulsory(cold)miss: location has never been accessed. • Capacity miss: working set is too large. • Conflict miss: multiple locations in working set map to same cache entry. Principles of Embedded Computing System Design

  6. Memory system performance • h = cache hit rate. • tcache = cache access time, tmain = main memory access time. • Average memory access time: • tav = htcache + (1-h)tmain Principles of Embedded Computing System Design

  7. Main memory L2 cache L1 cache CPU Multiple levels of cache Capacity increment Principles of Embedded Computing System Design

  8. Multi-level cache access time • h1 = cache hit rate. • h2 = rate for miss on L1, hit on L2. • Average memory access time: • tav = h1tL1 + (h2-h1)tL2 + (1- h2-h1)tmain Principles of Embedded Computing System Design

  9. Cache performance benefits • Keep frequently-accessed locations in fast cache. • Cache retrieves more than one word at a time. • Sequential accesses are faster after first access. Principles of Embedded Computing System Design

  10. Replacement policies (P.85) • Replacement policy: strategy for choosing which cache entry to throw out to make room for a new memory location. • Two popular strategies: • Random. • Least-recently used (LRU). Principles of Embedded Computing System Design

  11. Cache organizations (P.85) • Fully-associative: any memory location can be stored anywhere in the cache (almost never implemented). • Direct-mapped: each memory location maps onto exactly one cache entry. • N-way set-associative: each memory location can go into one of n sets. Principles of Embedded Computing System Design

  12. valid tag data 1 0xabcd byte byte byte ... cache block address tag index offset = value hit value Direct-mapped cache (P.86) Principles of Embedded Computing System Design

  13. Write operations • Write-through: immediately copy write to main memory. • Write-back: write to main memory only when location is removed from cache. Principles of Embedded Computing System Design

  14. Direct-mapped cache locations • Many locations map onto the same cache block. • Conflict misses are easy to generate: • Array a[] uses locations 0, 1, 2, … • Array b[] uses locations 1024, 1025, 1026, … • Operation a[i] + b[i] generates conflict misses. Principles of Embedded Computing System Design

  15. Set 1 Set 2 Set n ... set select hit data Set-associative cache • A set of direct-mapped caches: Principles of Embedded Computing System Design

  16. address data 000 0101 001 1111 010 0000 011 0110 100 1000 101 0001 110 1010 111 0100 Example: direct-mapped vs. set-associative (p.87) Principles of Embedded Computing System Design

  17. After 001 access: block tag data 00 - - 01 0 1111 10 - - 11 - - After 010 access: block tag data 00 - - 01 0 1111 10 0 0000 11 - - Direct-mapped cache behavior Principles of Embedded Computing System Design

  18. After 011 access: block tag data 00 - - 01 0 1111 10 0 0000 11 0 0110 After 100 access: block tag data 00 1 1000 01 0 1111 10 0 0000 11 0 0110 Direct-mapped cache behavior, cont’d. Principles of Embedded Computing System Design

  19. After 101 access: block tag data 00 1 1000 01 1 0001 10 0 0000 11 0 0110 After 111 access: block tag data 00 1 1000 01 1 0001 10 0 0000 11 1 0100 Direct-mapped cache behavior, cont’d. Principles of Embedded Computing System Design

  20. 2-way set-associtive cache behavior • Final state of cache (twice as big as direct-mapped): set blk 0 tag blk 0 data blk 1 tag blk 1 data 00 1 1000 - - 01 0 1111 1 0001 10 0 0000 - - 11 0 0110 1 0100 LRU replacement policy Principles of Embedded Computing System Design

  21. 2-way set-associative cache behavior • Final state of cache (same size as direct-mapped): set blk 0 tag blk 0 data blk 1 tag blk 1 data 0 01 0000 10 1000 1 10 0001 11 0100 Principles of Embedded Computing System Design

  22. Example caches (P.88) • StrongARM: • 16 Kbyte, 32-way, 32-byte block instruction cache. • 16 Kbyte, 32-way, 32-byte block data cache (write-back). • SHARC: • 32-instruction, 2-way instruction cache. Principles of Embedded Computing System Design

  23. logical address physical address MMU exchange CPU main memory storage data with/without storage Memory management units (P.89) • Memory management unit (MMU) translates addresses: Memory mapping Principles of Embedded Computing System Design

  24. Memory management tasks • Allows programs to move in physical memory during execution. • Allows virtual memory: • memory images kept in secondary storage; • images returned to main memory on demand during execution. • Page fault: request for location not resident in memory. Principles of Embedded Computing System Design

  25. Address translation • Requires some sort of register/table to allow arbitrary mappings of logical to physical addresses. • Two basic schemes: • segmented; • paged. • Segmentation and paging can be combined (x86). Principles of Embedded Computing System Design

  26. memory segment 1 page 1 page 2 segment 2 Segments and pages (P.90) Physical memory segment register offset/logical address Principles of Embedded Computing System Design

  27. instruction segment register segment base address logical address + range error segment lower bound range check segment upper bound physical address Segment address translation Principles of Embedded Computing System Design

  28. Logical address page number offset page i base concatenate page address offset page table Physical address Page address translation Principles of Embedded Computing System Design

  29. page descriptor i page descriptor flat tree Page table organizations Principles of Embedded Computing System Design

  30. Caching address translations • Large translation tables require main memory access. • TLB (translation lookaside buffer): cache for address translation. • Typically small. Principles of Embedded Computing System Design

  31. ARM memory management (P.92) • Memory region types: • section: 1 Mbyte block; • large page: 64 kbytes; • small page: 4 kbytes. • An address is marked as section-mapped or page-mapped. • Two-level translation scheme. Principles of Embedded Computing System Design

  32. Virtual address Translation table base register 1st index 2nd index offset descriptor 2nd level table pointer concatenate 1st level table descriptor page i base address concatenate 2nd level table physical address ARM address translation Principles of Embedded Computing System Design

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