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Integrated Circuits and Systems Laboratory Darmstadt University of Technology

Integrated Circuits and Systems Laboratory Darmstadt University of Technology. Design Space Exploration of incompletely specified Embedded Systems by Genetic Algorithm. Stephan Klaus Ralf Laue Sorin Alexander Huss Integrated Circuits and System Laboratory Department of Computer Science

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Integrated Circuits and Systems Laboratory Darmstadt University of Technology

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  1. Integrated Circuits and Systems LaboratoryDarmstadt University of Technology Design Space Exploration of incompletely specified Embedded Systems by Genetic Algorithm Stephan Klaus Ralf Laue Sorin Alexander Huss Integrated Circuits and System Laboratory Department of Computer Science Technische Universität Darmstadt Germany

  2. Outline • Motivation • Specification Model • Genetic Design Space Exploration • Application Example • Conclusion

  3. Motivation • Embedded Systems • Real-time and costs requirements • Different areas of application • Growing complexity • Shorter design cycles Embedded Systems are no longer designed from scratch, but partly from existing modules • System Level Design • Determine needed tasks • Determine suited architecture • Map complex tasks to architecture • Implementation consists of: Allocation, Binding, Scheduling

  4. Incomplete Specifications • Implementation consisting of • already existing modules (known execution properties) • a few custom made modules (unknown execution properties: no runtime estimations possible before HW/SW design decisions) Design Process with unknown execution properties necessary • Determine maximal execution times for new modules considering deadlines and known modules • The implementation of new modules can take place according to the determined maximal execution times

  5. Solution Objective 2 Pareto Front Objective 1 Design Space Exploration Goal: Determine suited implementation alternatives consideringlatency and costs Multi-Objective Optimization Problem

  6. Specification Model Hierarchical CoDesign Model (hCDM) • Hierarchical Task Graph Structure • Data and Control-flow Information • Condition captures control-flow fork c=false c=true normal join

  7. Genetic Algorithm Initialize population • System Level Synthesis with genetic Algorithm • Multi-objective optimization • Suited for large and non-convex search spaces • Considers sets of solutions • No linear cost function necessary • One-pass optimisation Evaluate individuals Select individuals Mutate individuals Determines aset of Pareto optimal implementation alternatives(allocation, binding, schedule) alternatives includingmaximal execution times for new modules. Crossover individuals Stop criteria finish

  8. Genetic Representation

  9. Evaluation • To perform Pareto ranking of all goals: • Determine latency, cost and sum of maximal new execution times • Objectives: fulfill deadlines and minimize costs and maximize sum of execution times • Each Individual is rated by the amount of individuals which are dominated by it • The individuals with the highest values are preferred

  10. Timing Evaluation 1: while ReadySet not empty do 2: io = Find IO Rel. with highest priority 3: if New Control Path in io then 4: Spilt ReadSet according to new condition 5: Duplicate schedule 6: EvalTiming(ReadySet1, FinishedSet, c1) 7: EvalTiming(ReadySet2, FinishedSet, c2) 8: else 9: ReadySet erase io; FinishedSet insert io 10: Calculate earliest start time ts of io 11: if new task with unknown timing then 12: texec = Get timing of io from individual 13: else 14: texec = Get timing of io from resource 15: Schedule insert (io, ts, ts + texec,Cond) 16: ReadySet insert ready tasks 17: end if 18: end while

  11. Application Example Mobile Robot equipped with an optical navigation Overall deadline: 420ms

  12. First Implementation (c,F) US Dist Motor Reg Stop mC (c,T) Ca Stop Reg GUI Pic Path GUI PC Pos FPGA (c,F) RS232 (c,T) PCI time 0 100 200 300 400

  13. Second Implementation US Dist Stop Path (c,F) Reg mC Stop Ca Path (c,T) GUI Motor GUI (c,F) PC GUI (c,T) Pic New Module: Pos FPGA (c,F) RS232 (c,T) PCI time 0 100 200 300 400

  14. Conclusion • System Level Design Space Exploration by genetic Algorithm: • Determines completeimplementation alternatives (consisting of Allocation, Binding, Scheduling) • Considers incomplete specifications • Advantages: • No estimation of unknown execution times necessary • Maximal execution times for new modules • Leads to easier implementation of such modules

  15. Integrated Circuits and Systems LaboratoryDarmstadt University of Technology Design Space Exploration of incompletely specified Embedded Systems by Genetic Algorithm Stephan Klaus Ralf Laue Sorin Alexander Huss www.vlsi.informatik.tu-darmstadt.de klaus|laue|huss@iss.tu-darmstadt.de

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