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STT-RAM Test Chip #1

STT-RAM Test Chip #1. Weekly Status Report Date: Wed Oct-21-2009. Amr Amin Preeti Mulage UCLA CKY Group. Previous Action Items. Cell Design: Investigating LVT devices, 1.2V supply, boosted WL voltage  Done Sensitivity analysis  In progress ( need data about MTJ variations )

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STT-RAM Test Chip #1

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  1. STT-RAM Test Chip #1 Weekly Status Report Date: Wed Oct-21-2009 Amr Amin Preeti Mulage UCLA CKY Group

  2. Previous Action Items • Cell Design: • Investigating LVT devices, 1.2V supply, boosted WL voltage  Done • Sensitivity analysis  In progress (need data about MTJ variations) • Memory Array • Reference cells for current sensing  Done • Array schematic and layout  Done • Column MUX schematic  Done • Sense amp and “write” driver schematic  Done • Connecting Top Cell  In progress

  3. MTJ Design Space

  4. Available Sensing Signal • I-Sense: ΔISIG vs. TMR for different values of RON

  5. Available Sensing Signal • I-Sense: Contours of constant ΔISIG in the MTJ Space

  6. Available Sensing Signal • V-Sense: ΔVSIG vs. TMR for different values of RP

  7. Available Sensing Signal • V-Sense: Contours of constant ΔVSIG in the MTJ Space

  8. Sense Amp Schematic

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