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STT-RAM Circuit Design

STT-RAM Circuit Design. Max I WRITE (Recap), MTJ Sharing Paper. Cell Sizing. Max I WRITE for I-STT (IBM65). I-STT MTJ Specs (Jianping). For 1ns switching: R P ≈ 500 Ω TMR ≈ 120% AP→P: 380-460 μ A P→AP: 600-800 μ A I WRITE(P→AP) /I WRITE(AP→P) : 1.5-2 I READ,MAX :

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STT-RAM Circuit Design

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  1. STT-RAM Circuit Design Max IWRITE (Recap), MTJ Sharing Paper

  2. Cell Sizing Max IWRITE for I-STT (IBM65)

  3. I-STT MTJ Specs (Jianping) • For 1ns switching: • RP ≈ 500Ω • TMR ≈ 120% • AP→P: 380-460μA • P→AP: 600-800μA • IWRITE(P→AP)/IWRITE(AP→P): 1.5-2 • IREAD,MAX: • If both the read and write pulses are on the order of a few ns, then IREAD/IWRITE ≈ 2/3. • We can share access transistors! (MAYBE) • Limiting factor in MTJ sharing is TMR degradation

  4. Minimum Cell Size (NN Corner) • VBS = -0.25V • Nominal • 37–45.5F2 • LVT • 33–40F2 • VBS = 0.00V • Nominal • 36–44F2 • LVT • 32.5–39.5F2

  5. Maximum Write Currents • 2 Cases: • VDD = 1V, WL = 1V • Nominal voltages specified in documentation • VDD & VWL is boosted (while keeping VDS, VGS < 1V) • Different VBL & VSL used to write “1” & “0” • IWRITE(P→AP)/IWRITE(AP→P): 1.5-2 • Example: • VWL = 1.10V • VBL<1> = 0.00V • VSL<1> = 1.10V • VBL<2> = 0.10V • VSL<2> = 1.40V • IWRITE: • AP→P = 335μA • P→AP = 670μA RP SL<1> BL<2> IWRITE (AP→P) IWRITE (P→AP) RAP WL<N> WL<N> BL<1> SL<2>

  6. Simulation Results (P→AP) • MTJ Specs: • RP = 500Ω • TMR = 120% IWRITE (P->AP) [μA] • NOMINAL VT • 25F2: VWL = 1.00V, VSL = 0.00V, VBL = 1.20V • 35F2: VWL = 1.10V, VSL = 0.10V, VBL = 1.35V • 50F2: VWL = 1.25V, VSL = 0.25V, VBL = 1.65V • LOW VT • 25F2: VWL = 1.00V, VSL = 0.00V, VBL = 1.20V • 35F2: VWL = 1.10V, VSL = 0.10V, VBL = 1.40V • 50F2: VWL = 1.30V, VSL = 0.30V, VBL = 1.80V

  7. Simulation Results (AP→P) • MTJ Specs: • RP = 500Ω • TMR = 120% IWRITE (AP->P) [μA] • NOMINAL VT • 25F2: VWL = 1.00V, VSL = 1.00V, VBL = 0.00V • 35F2: VWL = 1.10V, VSL = 1.10V, VBL = 0.00V • 50F2: VWL = 1.25V, VSL = 1.25V, VBL = 0.00V • LOW VT • 25F2: VWL = 1.00V, VSL = 1.00V, VBL = 0.00V • 35F2: VWL = 1.10V, VSL = 1.10V, VBL = 0.00V • 50F2: VWL = 1.30V, VSL = 1.30V, VBL = 0.00V

  8. Summary • Maximum IWRITE (LVT, FF) (P→AP) : • 25F2: 453.3μA • 35F2: 748.8μA • 50F2: 1183μA • Maximum IWRITE (LVT, FF) (AP→P) : • 25F2: 243.2μA • 35F2: 358.9μA • 50F2: 545.2μA • 35F2 LVT cell almost meets I-STT specs for 1ns switching • AP→P current a little weak (can be adjusted a little higher) • 38-40F2 LVT cell w/ boosted voltages can safely meet Jianping’s spec for 1ns switching

  9. MTJ Sharing TMR Degradation (Reading)

  10. TMR Degradation SL BL<M> BL<2> BL<1> Parallel Resistance (R||) degrades TMR WL<2> WL<N> WL<1> Parasitic Parallel Resistance MTJ1,1 MTJ1,2 MTJ1,M MTJN,M MTJ2,1 MTJ2,2 MTJ2,M MTJN,2 MTJN,1

  11. Effective RP and RAP • Worst case TMR’: largest RP’ and smallest RAP’ • Largest RP’: • Smallest RAP’

  12. Effective TMR (1) • Putting it all together: Example 1kbit Arrays: • TMR = 120%, M = 2, N = 16, 32-bit words: TMR’ = 4.8% • TMR = 120%, M = 2, N = 8, 64-bit words: TMR’ = 9.8% • TMR = 120%, M = 2, N = 4, 128-bit words: TMR’ = 20.7%

  13. TMR’ vs. N for 1T-2MTJ (M = 2)

  14. TMR’ vs. N for 1T-3MTJ (M = 3)

  15. Monte Carlo Simulations (1) • Limited to M = 2 • Theoretical TMR’ is overly pessimistic • With error correction we can let the extreme cases fail. • Example: • Bit read error = 0.1% • Word length = 64 • # error correcting bits = 4 • Probability of a word error: 1 in 137,763,712 reads • M = 2, N = 4 • TMR = 120%, RP = 500Ω • 25k Simulations • Worst Case TMR’ • Theoretical = 20.7% • Simulation = 46.2%

  16. Monte Carlo Simulations (2) • M = 2, N = 8 • TMR = 120%, RP = 500Ω • 25k Simulations • Worst Case TMR’ • Theoretical = 9.8% • Simulation = 20.7% • M = 2, N = 16 • TMR = 120%, RP = 500Ω • 25k Simulations • Worst Case TMR’ • Theoretical = 4.8% • Simulation = 10.1%

  17. MTJ Sharing Device IREAD/IWRITE Requirements (Writing)

  18. Defining IREAD,MAX & IWRITE,MIN • IREAD,MAX: The maximum read current such that the probability of flipping the MTJ is less than some ε(i.e. ε = 0.1% → IREAD,MAX = 200μA) • IWRITE,MIN: The minimum write current such that the probability of failing to flip the MTJ is less than some ξ(i.e. ξ = 0.1% → IWRITE,MIN = 600μA)

  19. IREAD/IWRITE for 1T-2MTJ (1) BL<1> • Limited to 1T-2MTJ architecture WL<2> WL<1> BL<2> IWRITE,MIN α∙IREAD,MAX

  20. IREAD/IWRITE for 1T-2MTJ (2) RP Case 1: RAP Case 1: RP Case 2: RAP Case 2: “1” “1” “1” “1” “0” “0” “0” “0” RAP RP RAP RP RP RP RP RAP RP RAP RP RAP RP RP RAP RP

  21. IREAD/IWRITE vs. TMR

  22. SUMMARY • Cell Sizing: 35-40F2 • TMR Degradation: M = 2 (READING) • Word length should be greater than 64 • Serious TMR degradation for N > 8 • Ideally: • RP = 500Ω, TMR = 120% • M = 2, N = 4 → 1kbit arrays of 128-bit words • TMR’ = 20.7% • Reality: TMR’ ≈ 45% (ignoring worst case) • Need less than 8 error correcting bits • IREAD/IWRITE (WRITING) • For TMR = 120%, χ = 1.5-2: IREAD/IWRITE > 0.36-0.43

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