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STT-RAM Test Chip #1

STT-RAM Test Chip #1. Weekly Status Report Date: Wed Nov-04-2009. Amr Amin Preeti Mulage UCLA CKY Group. Remaining Tasks. SA offset and min “read” signal Using VA model for the MTJ (Preeti) Simulating the “write” circuit (Preeti) Adjusting the Addressing Logic

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STT-RAM Test Chip #1

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  1. STT-RAM Test Chip #1 Weekly Status Report Date: Wed Nov-04-2009 Amr Amin Preeti Mulage UCLA CKY Group

  2. Remaining Tasks • SA offset and min “read” signal • Using VA model for the MTJ (Preeti) • Simulating the “write” circuit (Preeti) • Adjusting the Addressing Logic • Adding the dummy poly resistors and extra MUXs (Amr) • Adding logic for testing (Amr) • Adjusting timing and control • Using an un-clocked amp instead of the latch • Scan Chain synthesis (Yuta and Preeti) • Top cell integration (Amr) • Chip Sim with package model (Amr and Preeti) • Layout (Amr and Preeti) • Post layout sim (Amr and Preeti) • Tapeout !

  3. Memory Array Revisited • What should be…

  4. Memory Array Revisited • What we have…

  5. Memory Array Revisited • Adding dummy resistors: • The easy way • Each resistor can have a different value • Reference resistance will be constant

  6. Memory Array Revisited • Adding dummy resistors: • One variable conductance for each half-bank • Can help having a variable reference • Same Column-Select Signals can be used for both MUXs • Resistance programming bits should come from the scan-chain

  7. Memory Array Revisited • Combination of the previous two solutions • Fixed resistance for each column • One variable resistance for the reference • Testing MUX allows each resistor to be measured • Programming bits and Test MUX controls should come from the scan-chain

  8. Operation Modes • Still working on defining the chip operation modes and writing a truth table for the allowed combinations of control bits

  9. Port List

  10. Port List

  11. Port List

  12. Pad List

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