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Enhanced Cluster Processor Chip Design for High-Speed Data Capture and Processing

This document details the requirements and configurations for a Cluster Processor Chip (CPC) designed to handle multiplexed data at 160 Mbit/s. It outlines the processes for capturing, synchronizing, and performing BC de-multiplexing with error checking. The CPC integrates various logic blocks, including serial to parallel conversion and algorithmic processing of Cluster Hits and Regions of Interest (RoIs). Additionally, a second configuration for setup and diagnostic logic is discussed, emphasizing future simulation needs and the deployment of test vectors.

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Enhanced Cluster Processor Chip Design for High-Speed Data Capture and Processing

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  1. Cluster Processor Chip • Requirements • Process 4 x 2 x 2 TT Window • Receive BC multiplexed data • 108 at 160 Mbit/s • Capture and synchronise • BC-De mux and error checking • e/g, t/h Algorithm • Cluster Hits • RoIs • Readout of RoIs

  2. Cluster Processor Chip • Requirements • Set-up and diagnostic Logic (second configuration)

  3. Cluster Processor Chip • CP Chip Status • All logic blocks designed and integrated • Serial to Parallel conversion and Synchronisation • BCID De-multiplexing logic • Algorithm • Readout logic • Set-up and diagnostic logic implemented as a second configuration • More simulations to be done • Test vectors supplied by Steve Hillier

  4. Cluster Processor Chip • Device • Fits in XCV1000E-6 • Latency • Seven, 40 MHz clock ticks (-6 device)

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