1 / 12

ISA – Chapter 1.7 (CD) MIPS – Chapter 2

ISA – Chapter 1.7 (CD) MIPS – Chapter 2. HW/SW facts. Large hardware structures More expensive (yield, #dies per wafer) Slower to use each time (phone book) Holds more Large instruction size More memory required Each one is slower Each one does more Fewer instructions per program

britain
Télécharger la présentation

ISA – Chapter 1.7 (CD) MIPS – Chapter 2

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. ISA – Chapter 1.7 (CD)MIPS – Chapter 2

  2. HW/SW facts • Large hardware structures • More expensive (yield, #dies per wafer) • Slower to use each time (phone book) • Holds more • Large instruction size • More memory required • Each one is slower • Each one does more • Fewer instructions per program • Processor fast … Memory slow

  3. . . ALU Source1 ALU Source 2 (if different from dest) ALU dest . . Stack Processor • “Stack” is internal to the processor. • ALU operates on top two stack items • Remove two top values • Place result on the top of the stack • Memory operation: • Explicit push & pop for memory • RPN calculators are stack machines • Java JVM is stack-based TOS . . D = A * B + C Memory

  4. ALU Source1 ALU Source 2 (if different from dest) ALU dest Accumulator Processor Only one register ALU inputs: accumulator & memory Memory Operations: explicit load & store one operand of alu operations . . D = A * B + C Memory . . . .

  5. ALU Source1 ALU Source 2 (if different from dest) ALU dest Register (register-memory) Processor ALU inputs: register & memory Memory operations: Explicit load & store One operand of ALU operations . . D = A * B + C Memory . . . .

  6. . . ALU Source1 ALU Source 2 (if different from dest) ALU dest Register (load-store) Processor ALU inputs: Two registers Memory access: Only through load & store D = A * B + C Memory . . . .

  7. Core Differences Reg-Reg Stack Accumulator Reg-Mem • Which access memory every instruction? • Which have access to any values inside the processor at any time? TOS . . . . . . . . Memory Memory

  8. Summary • Registers are _____ – Memory is ______ • Instruction reordering is important for __________ • Leads to __________________ architectures • Was this always the case? Why were the others ever built?

  9. MIPS Assembly Language • Load-Store architecture • Arithmetic ops only on regs • Reads <= two regs per instruction • Writes <= one reg per instruction • Simple instructions • 32 total registers

  10. Arithmetic Operations • add $2, $3, $5 ------ $2 = $3 + $5 • destination is first • add, sub, addu, subu (unsigned) • and, or, xor • addi $2, $3, 10 ------ $2 = $3 + 10 • destination is first • “immediate value” (constant) encoded into inst • andi, ori, xori, • sll (shift left logical) , srl (shift right logical)

  11. Multiply, Divide: Using the Co-Processor • mult $s2, $s3 -- HI, LO = $s2 * $s3 • div $s2, $s3 - LO = $s2 / $s3, HI = $s2 % $s3 • mfhi $s1 -- $s1 = HI • mflo $s1 -- $s1 = LO $s1 = $s2 * $s3 mult $s2, $s3 mflo $s1 $s1 = $s2 / $s3 div $s2, $s3 mflo $s1 $s1 = $s2 % $s3 div $s2, $s3 mfhi $s1

  12. Multiply, Divide:Using simple operations Exploiting binary numbers • $s2 = $s1 * 2n == ____________ • ____________ • $s2 = $s1 / 2n == ____________ • ____________ • $s2 = $s1 % 2n == ____________ • ____________

More Related