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Intro to Timing analysis via the timequest timing analyzer

Intro to Timing analysis via the timequest timing analyzer. By Waleed Atallah and Larry Landis. Objective. You will learn the fundamental theory behind timing analysis including: Key terminology Math behind timing analysis Setup and Hold Slack equations with exercises

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Intro to Timing analysis via the timequest timing analyzer

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  1. Intro to Timing analysis via the timequest timing analyzer By Waleed Atallah and Larry Landis

  2. Objective • You will learn the fundamental theory behind timing analysis including: • Key terminology • Math behind timing analysis • Setup and Hold Slack equations with exercises • How timing constraints are described in Quartus (.SDC files) • Creating I/O Constraints with exercises • Other terms and considerations

  3. Requirements • You will need: • Basic background in digital logic • Quartus Prime 17.0 lite or newer • Materials: • Lab Document: http://www.alterawiki.com/wiki/File:TimingAnalysisLab.pdf • Slides: http://www.alterawiki.com/wiki/File:TimeQuest_class.pptx

  4. Part 1Timing analysis fundamentals Key terms, definitions, and math

  5. Why Semiconductors Fail • Many Opinions ... Here are some • Functionally Incorrect • Bad Timing Constraints (* or no timing constraints) • Didn’t follow manufacturing guidelines (LVS, DRC) • Test Escapes • Too much power consumption • Signal Integrity • Crosstalk • Wearout mechanisms

  6. What effects circuit timing? • Length of wire • R and C of wire • Logic depth of the path • Size of the transistors • Process - deposition • Voltage • Temperature Some logic depicting different depths of paths

  7. “Timing Arc” • It takes a finite time for an input to effect an output change • Very often tphl and tplh can be different amounts of time

  8. Terminology • Types of paths that TimeQuest analyzes • Data Paths: Paths a signal travels betweeninputs, sequential elements, and outputs • Clock Paths: Paths from device ports or internally generated clocks to the clock pins of sequential elements • Asynchronous Paths: Paths betweeninput port and asynchronous set or clear pin of a sequential element.Used in recovery and removal checks

  9. Timing Paths Three Data Path Types • From input to a sequential element • From sequential element to sequential element • From sequential element to output Data Path

  10. Setup and Hold Time • Setup: • The minimum time the data signal must be stable BEFORE the clock edge • Hold: • The minimum time the data signal must be stable AFTER the clock edge Data Valid Window: the range of time around the clock edge in which data must remain stable to be properly captured

  11. Example of Data Settling in Gate Level Simulation

  12. Launch and Latch Edge • Launch Edge: the clock edge that activates or launches the source register • Latch Edge: the clock edge that latches the data into the destination register Data

  13. Data and Clock Arrival Time • Data Arrival Time (DAT): the time it takes for the data to arrive at the destination register input • Clock Arrival Time (Tclk): the time it takes for the clock to arrive at the destination register • Clock to Out Time (tco): the time it takes for a signal to propagate out after a clock edge

  14. Data Arrival Time tdata tdata

  15. Clock Arrival Time

  16. Data Required Time • Data Required Time (setup): the minimum time required BEFORE the latch edge for data to get latched into the destination register = Clock Arrival Time – Setup Time • Data Required Time (hold): the minimum time required AFTER the latch edge for the data to remain valid for successful latching = Clock Arrival Time + Hold Time Image Caption 10pt gray text

  17. Data Required Time (setup) • Data Required Time (setup) = Clock Arrival Time – Setup Time

  18. Data Required Time (hold) • Data Required Time (hold) = Clock Arrival Time + Hold Time

  19. Setup Slack tdata Setup slack = minimum data required time – max data arrival time tco Tclk1 tco Data Valid Data Valid tdata Dependent on frequency!

  20. Hold Slack tdata Hold slack = minimum data arrival time – max data required time tdata NOT dependent on frequency!

  21. Math • Test Yourself! • Setup slack = (a) min data req time (setup) – max data arrival time (b) max data req time (setup) – min data arrival time (c) min data req time (hold) – max data req time (setup) (d) max data arrival time – min data req time (hold)

  22. Math • Test Yourself! • Setup slack = (a) min data req time (setup) – max data arrival time (b) max data req time (setup) – min data arrival time (c) min data req time (hold) – max data req time (setup) (d) max data arrival time – min data req time (hold)

  23. Review • Remember these three lines and you’ll always know how to calculate slack • Slack = min <something> - max <something> • Setup = min DRT – max DAT • Hold = min DAT – max DRT

  24. Example: Setup T = 20 ns 50 MHz Setup slack: min delay along clock path – max delay along data path = (min data required time) (max data arrival time)

  25. Example: Setup T = 20 ns 50 MHz Setup slack: min delay along clock path – max delay along data path = Setup slack: min delay along clock path – max delay along data path = (20+2+5+2-4) - (min data required time) (max data arrival time)

  26. Example: Setup T = 20 ns 50 MHz Setup slack: min delay along clock path – max delay along data path = (20+2+5+2-4) – (2+11+2+9+2) = 25-26 = -1ns Setup slack: min delay along clock path – max delay along data path = (min data required time) (max data arrival time)

  27. Example: Setup • Calculate Maximum Frequency • Setup Slack = -1 ns • Make the period 1 ns longer, 20+1 = new period = 21 ns • Tmin= DATmax + tsu– tclk,min = 26+4-9=21 ns = Data Arrival Time + setup time of destination reg – clock delay to destination reg • fmax= 1/Tmin = 1/21 = 47.6 MHz T = 20 ns 50 MHz Setup slack: min delay along clock path – max delay along data path = 25 – 26 = -1 ns

  28. Example: Hold T = 20 ns 50 MHz Hold slack: min delay along data path – max delay along clock path = (min data arrival time) (max data required time)

  29. Example: Hold T = 20 ns 50 MHz Hold slack: min delay along data path – max delay along clock path = (1+9+1+6+1) – (min data arrival time) (max data required time)

  30. Example: Hold T = 20 ns 50 MHz Hold slack: min delay along data path – max delay along clock path = (1+9+1+6+1) – (3+9+3+2) = 18-17 = 1 ns (min data arrival time) (max data required time)

  31. Exercise one End of Part 1

  32. Problem • Exercise 1(a) • Setup Slack = min DRT – max DAT = T = 10 ns

  33. Solution • Exercise 1(a) • Setup Slack = min DRT – max DAT = (10 + 1 + 1 - 2) T = 10 ns

  34. Solution • Exercise 1(a) • Setup Slack = min DRT – max DAT = (10 + 1 + 1 - 2) – (1 + 2 + 5) = 2 ns T = 10 ns

  35. Solution • Exercise 1(a) • Setup Slack = min DRT – max DAT = (10 + 1 + 1 - 2) – (1 + 2 + 5) = 2 ns • Hold Slack = min DAT – max DRT = T = 10 ns

  36. Solution • Exercise 1(a) • Setup Slack = min DRT – max DAT = (10 + 1 + 1 - 2) – (1 + 2 + 5) = 2 ns • Hold Slack = min DAT – max DRT = T = 10 ns

  37. Solution • Exercise 1(a) • Setup Slack = min DRT – max DAT = (10 + 1 + 1 - 2) – (1 + 2 + 5) = 2 ns • Hold Slack = min DAT – max DRT = (1 + 2 + 3) T = 10 ns

  38. Solution • Exercise 1(a) • Setup Slack = min DRT – max DAT = (10 + 1 + 1 - 2) – (1 + 2 + 5) = 2 ns • Hold Slack = min DAT – max DRT = (1 + 2 + 3) – (1 + 1 + 1.5) = 2.5 ns T = 10 ns

  39. Solution • Exercise 1(b) • Setup Slack = min DRT – max DAT = • Hold Slack = min DAT – max DRT = T = 6.6 ns

  40. Solution • Exercise 1(b) • Setup Slack = min DRT – max DAT = (6.6 + 1 + 1 - 2) – (1 + 2 + 5) = -1.4 (Fails!) • Hold Slack = min DAT – max DRT = T = 6.6 ns

  41. Solution • Exercise 1(b) • Setup Slack = min DRT – max DAT = (6.6 + 1 + 1 - 2) – (1 + 2 + 5) = -1.4 (Fails!) • Hold Slack = min DAT – max DRT = (6.6 + 1 + 2 + 3) – (6.6 + 1 + 1 + 1.5) = 2.5 ns(Doesn’t change!) T = 6.6 ns

  42. Part 2Describing timing conStraints Synopsys Design Constraints, set_input_delay, set_output_delay

  43. Synopsys Design Constraints (SDC) • Synopsys Design Constraints are the industry standard for describing timing constraints and exceptions • Quartus Prime uses .SDC files to define clocks, I/O constraints, etc... The fitter needs this information to make the best decisions • You can make and edit these using the TimeQuest GUI or by editing the .sdc file in a text editor

  44. I/O Constraints • Using SDC, specify set_input_delay and set_output_delay Set_input_delay (min, max) Set_output_delay (min, max) NOTE: TW is wire delay, or board delay TCLK is clock delay Every value has both a maximum and minimum

  45. I/O Constraints • set_input_delay • Use this command to specify external delays feeding into the FPGA’s input ports • set_input_delaymin = min clock-to-out of ext chip + min board delay – max clock skew = TCO,MIN + TW1,MIN – (TCLK1,MAX – TCLK2,MIN) • set_input_delaymax = max clock-to-out of ext chip + max board delay – min clock skew = TCO,MAX + TW1,MAX – (TCLK1,MIN – TCLK2,MAX) • set_input_delay [-add_delay] -clock <name> [-clock_fall] [-fall] [-max] [-min] [-reference_pin <name>] [-rise] [-source_latency_included] <delay> <targets>

  46. I/O Constraints • set_output_delay • Use this command to specify external delays leaving the FPGA’s output ports • set_output_delaymin = -(min hold time of ext chip) + min board delay – max clock skew = -Th,MIN+ TW2,MIN – (TCLK3,MAX – TCLK1,MIN) • set_output_delaymax = max setup time of ext chip + max board delay – min clock skew = TSU,MAX + TW2,MAX – (TCLK3,MIN – TCLK1,MAX) • set_output_delay [-add_delay] -clock <name> [-clock_fall] [-fall] [-max] [-min][-reference_pin <name>] [-rise] [-source_latency_included] <delay> <targets>

  47. I/O Constraints • Check the datasheets

  48. External Signals and your FPGA • Check the datasheets!

  49. I/O Constraints • Example • set_input_delaymin = TCO,MIN + TW1,MIN – (TCLK1,MAX – TCLK2,MIN) = Tw1 = 4 ± 1.0 ns Tw2 = 3 ± 0.5 ns Tsu = 2ns Th = 3 ns Tco = 3 ±1.0 ns Tclk1 = 1.0 ± 0.5 ns Tclk2 = 1.5 ± 0.5 ns Tclk3 = 1.5 ± 1.0 ns

  50. I/O Constraints • Example • set_input_delaymin = TCO,MIN + TW1,MIN – (TCLK1,MAX – TCLK2,MIN) = 2 + 3 – (1.5 – 1) = 4.5 ns Tw1 = 4 ± 1.0 ns Tw2 = 3 ± 0.5 ns Tsu = 2ns Th = 3 ns Tco = 3 ±1.0 ns From data sheet! Tclk1 = 1.0 ± 0.5 ns Tclk2 = 1.5 ± 0.5 ns Tclk3 = 1.5 ± 1.0 ns

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