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State-identification Experiments and Testing of Sequential Circuits

State-identification Experiments and Testing of Sequential Circuits. Experiments. Experiment: application of an input sequence to the input terminals of a machine Simple: performed on a single copy Multiple: performed on two or more identical copies

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State-identification Experiments and Testing of Sequential Circuits

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  1. State-identification Experiments and Testing of Sequential Circuits

  2. Experiments Experiment: application of an input sequence to the input terminals of a machine • Simple: performed on a single copy • Multiple: performed on two or more identical copies • Adaptive: input symbol at any time instant depends on previous output symbols • Preset: entire input sequence is predetermined • Length: total number of symbols in the experiment Checking experiment: designed to take the machine through all its transitions to ascertain if it is working correctly

  3. Introductory Example Example: Consider machine M1 and its responses to 01 and 111 • Output response to 01: uniquely determines the machine’s final state, but not the initial state • Output response to 111: uniquely determines the machine’s final and initial states

  4. Uncertainties Initial uncertainty: minimal subset of set of states S, which is known to contain the initial state • For machine M1: (ABCD) If application of input symbol 1 results in output symbol 1: uncertainty is (ACD) • 1-successors of (ACD):uncertainty vector (B)(CD) • Components of uncertainty vector: (B) and (CD) • Trivial uncertainty vector: all components have a single state • Homogeneous uncertainty vector: components contain a single state or identical repeated states

  5. Successor Tree Successor tree: displays Ii-successor uncertainties for all Ii • Path: sequence of j branches starting at the highest node and terminating at the jth level • Length of the path:j • Each path describes: an input sequence

  6. Homing Experiments An input sequence Y0 is a homing sequence if the final state of the machine can be determined uniquely from the machine’s response to Y0, regardless of the initial state Homing tree: successor tree in which a jth-level node becomes terminal when: • It is associated with an uncertainty vector whose non-homogeneous components are associated with some node in a preceding level • It is associated with a trivial or homogeneous vector Example: Consider machine M2 Theorem: A preset homing sequence of length at most (n-1)2 exists for every reduced n-state machine

  7. Synchronizing Experiments A synchronizing sequence of a machine M is an input sequence that takes M to a specified final state, regardless of the outputs symbols or the initial state In a synchronizing tree: a jth-level node becomes terminal whenever: • The node is associated with an uncertainty that is also associated with some node in a preceding level • Some node in the jth level is associated with an uncertainty containing just a single element Example: Machine M2 and its synchronizing tree Theorem: If a synchronizing sequence for an n-state machine M exists, then its length is at most (n-1)2n/2

  8. Distinguishing Experiments An input sequence X0 of machine M is said to be a distinguishing sequence if the resulting output sequence is different for each initial state • Since the knowledge of the initial state and input sequence is always sufficient to uniquely determine the final state: every distinguishing sequence is also a homing sequence • The converse is not true Distinguishing tree: successor tree in which a node at the jth level becomes terminal when: • The node is associated with an uncertainty vector whose non-homogeneous components are associated with some node in a preceding level • The node is associated with an uncertainty vector containing a homogeneous nontrivial component • Some node at the jth level is associated with a trivial uncertainty vector

  9. Distinguishing Experiments (Contd.) Example: Machine M1 and its distinguishing tree Example: While every machine has a homing sequence, not every machine has a distinguishing sequence – Consider M2 and its distinguishing tree

  10. Shortest Distinguishing Prefix Example: Consider machine M1 and its response to 111 • Shortest distinguishing prefix for state C: 1 • For state D: 11 • For states A and B: 111

  11. Machine Identification Machine identification: experimentally determining the state table of an unknown machine • Input alphabet known • Upper bound on the number of states known • Machine must be reduced and strongly connected Example: Suppose a machine is supposed to have two states and its response to input sequence X is output sequence Z: • Corresponding machine M3:

  12. Checking Experiments Given a machine and its state table: determine from terminal experiments whether the actual machine is isomorphic to the one described by the state table • Machine assumed to be: strongly connected, completely specified and reduced • Faults assumed to be: permanent • Machine either has a synchronizing sequence: or a reset input exists that will transfer it to the initial state • Initial assumption: a distinguishing sequence exists Designing checking experiments: two parts • Use the synchronizing sequence or reset input to transfer the machine into a prespecified state: initial state for the second part of the experiment • Preset experiment: take machine through all possible transitions • Machine is caused to display the response of each of its states to the distinguishing sequence • Then, actual state transitions are verified

  13. Example Example: Machine M4 and its responses to distinguishing sequences 00 and 01 • Suppose the synchronizing sequence or reset input places M4 into A • First ascertain: starting state is indeed A and the machine being tested actually contains four distinct states • Next: verify every state transition • Apply the input symbol corresponding to the transition • Identify it by applying the distinguishing sequence

  14. Example (Contd.) Example (contd.): First stage for checking all state transitions except those from D to A and A to B and C

  15. Example (Contd.) Example (contd.): Complete experiment:

  16. Design of Diagnosable Machines Diagnosable machine: one which possesses one or more distinguishing sequences Testing table and graph: for machine M2 that does not possess a distinguishing sequence Implied pair Uncertainty pair

  17. Definitely Diagnosable Machines A machine is definitely diagnosable machine of order if is the least integer s.t. every sequence of length is a distinguishing sequence for M • Every node in level of the distinguishing tree is associated with a trivial uncertainty vector Theorem: A machine is definitely diagnosable if and only if its testing graph G is loop-free and no repeated states exist in the testing table Corollary: Let the testing table of machine M be free of repeated entries, and let G be a loop-free testing graph for M • If the length of the longest path in G is l: then = l + 1

  18. Designing Definitely Diagnosable Machines Example: Obtaining definitely diagnosable M2’ from M2 • Assign different output symbols to each transition that may cause a repeated entry in the testing table • Open loops in the testing graph by removing one of the arcs

  19. Definitely Diagnosable Machines (Contd.) For any 2k-state machine: addition of k output terminals is sufficient to convert it into a definitely diagnosable machine

  20. State Table based Test Generation Functional fault model: faults assumed to be associated with a state transition • Single-state-transition (SST) fault model: fault results in the destination state of the state transition becoming corrupted while retaining its correct input/output symbols • Test generation based on SST faults: known to detect a very high percentage of single stuck-at faults in the sequential circuit • Assumption: SST fault does not increase the number of states in the state table • State transition designated as a four-tuple: <input symbol, source state, destination state, output symbol> • A state transition can become corrupted: if its destination state, output symbol or both are faulty • However, if a test sequence detects a corrupted destination state: then it also detects the corrupted output symbol or both the corrupted destination state and output symbol • Three parts to a test sequence: • Initialization sequence • Input symbol of the transition to activate the fault • State-pair differentiating sequence (SPDS)

  21. Test Generation (Contd.) Fault collapsing: An n-state m-transition machine has m(n-1) SST faults • For each state transition: there are n-1 faulty destination states possible • Suppose the four-tuple <Ik,Sj,Si,Ol> is corrupted to: <Ik,Sj,Si’,Ol> by SST fault f1 and to <Ik,Sj,Si’’,Ol> by SST fault f2 • If SPDS(Si,Si’) also differentiates between Si and Si’’: fault f2 dominates fault f1, and f2 can be removed from the fault list Example: Consider machine M5 • SPDS(A,B) = SPDS(A,C) = 0 and SPDS(B,C) = 1 • Consider <1,C,A,0>: can be corrupted to <1,C,B,0>, <1,C,C,0>, <1,C,D,0> • Since SPDS(A,B) = SPDS(A,C): the first two faulty transitions can be collapsed into just the first one

  22. Test Generation Example Example: Consider the SST fault that corrupts <0,D,A,0> to <0,D,B,0> • We first need transfer sequence T(A,D) = 00 (10 is also a valid sequence) • Fault is activated by x = 0 • Finally, SPDS(A,B) = 0 is applied • Hence, one possible test sequence: 0000

  23. Sequential Circuit based Test Generation Extended D-algorithm: • Target a fault in some time frame, say time frame 0 in the iterative array model: use D-algorithm to generate a test vector for it • If a D or D’ propagates to a circuit output: no further error propagation required • If D or D’ only propagates to next state lines: add new time frames to the right until the error signal reaches some circuit output • If test vector contains assignments of specific logic values to any present state lines in time frame 0: add new time frames to the left until no particular values are required on the present state lines

  24. Example Example: Test sequence for x2s-a-1: {(1,1),(1,0),(1, )}

  25. Nine-valued Logic Five-valued logic {0,1, ,D,D’} used in D-algorithm: not adequate for sequential circuits because it overspecifies the value requirements at some lines in the circuit • This may prevent the test generator from obtaining a test sequence even when one exists • This problem can be tackled by nine-valued logic: 0/0, 0/1, 0/ , 1/0, 1/1, 1/ , /0, /1, /

  26. Example Example: Unsuccessful test generation with five-valued logic

  27. Example (Contd.) Example (contd.): Successful test generation with nine-valued logic • Test sequence: {(0,0),(0,1)}

  28. Design for Testability Scan design for sequential circuits: two modes of operation • Normal mode: circuit exhibits original behavior • Test mode: its flip-flops are chained together into a shift register • Full-scan: all flip-flops are chained • Partial-scan: a subset of flip-flops are chained Scan flip-flop and its symbol: Scan chain: only combinational test generation needed

  29. Scan-based Test Application Application of the test set derived for the combinational logic to the sequential circuit: • Make T = 1 to set circuit into the test mode • Scan in the state part of the vector through the ScanIn input in the next k clock cycles. Primary inputs can be fed arbitrary values in these cycles • Apply the primary input part of the vector to the primary inputs. Now, all l+k bits of the test vector have been applied to the combinational logic. After allowing the logic to settle down, observe the output response at circuit outputs z1, z2, …, zm • Make T = 0 to set the circuit into the normal mode • Apply a clock pulse. This results in the values on the next state lines, Y1, Y2, …, Yk, being latched in the k flip-flops • Make T = 1 and observe the values captured in the flip-flops by scanning them out through ScanOut while repeating the procedure for the next test vector

  30. Testing of Scan Designs Suppose there are n test vectors in the test set • A total of k cycles required to scan in the state part • One cycle to capture state response • k-1 cycles required to scan out the captured state • Since the state part of the next state vector is scanned in at the same time the captured state for the previous vector is being scanned out: total no. of clock cycles required for testing =n(k+1)+k-1 Example: total no. of clock cycles = 4(2+1)+2-1 = 13

  31. Built-in Self-test (BIST) Integration of circuitry on-chip to enable the circuit under test (CUT) to test itself • At-speed testing possible: at the normal clock rate • Detects delay faults • Test pattern generator (TPG) • Response analyzer (RA): compresses output response into a signature • Golden signature: when no fault is present

  32. Test Pattern Generator TPG: usually a linear feedback shift register (LFSR) • LFSR with degree-kfeedback polynomial: p(x) = xk + b1xk-1 + … + bk-1x + bk • Outputs of the k flip-flops directly fed to inputs of a k-input CUT Example: Three-stage LFSR with p(x) = x3 + x2 + 1

  33. Feedback Polynomial A feedback polynomial is said to be primitive if the state diagram corresponding to the k-stage LFSR consists of two loops: • Trivial loop: with the all-0 state • Non-trivial loop: with the remaining 2k-1 states Example: State diagram of the three-stage LFSR based on p(x) = x3+x2+1 • Thus, p(x) is primitive

  34. LFSR Seed LFSRs based on primitive polynomials find use in BIST • Test pattern can start with any state in the non-trivial loop • Initial state: seed • LFSR re-seeding: Start from different seeds and apply a few test patterns from each in order to shorten the test application time Example: For the circuit below, possible stuck-at test set: (x3,x2,x1) = {(1,0,1), (1,1,1), (1,0,0), 0,1,0)} • Choose three-stage LFSR:yi connected to xi • Testing accomplished by: two patterns starting with seed (1,0,1) and two additional patterns starting with (1,0,0) • Alternative: six clock cycles from (1,0,1) to (0,1,0)

  35. Response Analyzer For a k-output CUT, to which n patterns have been applied by the TPG: need to analyze kn output bits to detect error • Storing these bits and performing bit-by-bit comparison to error-free values is expensive in space and time: • Thus, RAs used to compress the output response • Aliasing: Signature in the presence of a fault is the same as the golden signature • Typically, negligible aliasing probability = 1/2m Multiple-input signature register

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