Testing for whole function
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Testing for whole function. Previous To-Do. Add randomWait , UART into multiple rcvQ program Debug for sometimes sending twice in the same slot Caused by race condition of TBR, when checking valid time to send. Results.
Testing for whole function
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Presentation Transcript
Previous To-Do • Add randomWait, UART into multiple rcvQprogram • Debug for sometimes sending twice in the same slot • Caused by race condition of TBR, when checking valid time to send
Results • In 18-minute experiment , the clock drift is smaller than the biggest value 80 us (@13 min) for last data slot in every minute
UART • Had dumped the UART information, but not correctly calculate now, need to revise • RX is receiving from parent while TX is send to children, need to combine two hop info. to get correct value
To-Do • Get correct UART info to make sure whether crossing-slot problem occurs or not • Open CCA mechanism for CSMA to see the result
Appendix -2 Mins • 53 us
3 Mins • 47 us
4 Mins • 69 us
5 Mins • 69 us
6 Mins • 64 us
7 Mins • 45 us
8 Mins • 51 us
9 Mins • 58 us
10 Mins • 49 us
11 Mins • 62 us
12 Mins • 76 us
13 Mins • 80 us
14Mins • 47 us
15Mins • 44 us
16Mins • 73 us
17Mins • 26 us
18 Mins • 43 us
