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Low-Power Testing Techniques for System-on-Chip Design and Optimization

This document discusses advanced low-power testing techniques essential for System-on-Chip (SoC) design, emphasizing low-power Automatic Test Pattern Generation (ATPG) algorithms and vector compaction methods. It highlights the significance of clever don't-care bit assignment to minimize transitions during testing and explores ordering techniques to reduce switching activity. Additionally, it addresses clock scheme modifications to manage power dissipation in testing and the utilization of test data compression strategies to optimize test volume. These methodologies aim to enhance power efficiency while maintaining test effectiveness.

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Low-Power Testing Techniques for System-on-Chip Design and Optimization

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  1. EE 587SoC Design & Test Partha Pande School of EECS Washington State University pande@eecs.wsu.edu

  2. Low-Power Testing

  3. Low Power External Testing Techniques • Low Power ATPG algorithms • Ordering Techniques • Vector Compaction and data Compression • Clock Scheme Modification

  4. Low Power ATPG • Clever assignment of don’t-care bits minimizes the number of transitions that occur in the CUT between two consecutive test vectors • Exploit don’t cares that occurs during scan shifting, test application, and response capture

  5. Ordering Techniques • Reduce switching activity by modifying the order in which testers apply test vectors to the CUT • Use Hamming distance between test vectors rather than the number of transitions in the circuit to evaluate the switching activity produced in the CUT by a given input test pair • Modify the order in which scan flip flops are chained

  6. Test Data Compression • Use of test data compression • Reduce test data volume and scan power dissipation • compress precomputed test set provided by the core vendor, into the much smaller test set, which is stored in ATE memory

  7. Clock Scheme Modification • Test power’s major contributor is the clock tree • Generate and order test sets in such a way that some of the scan chains can have their clocks disabled for portions of the test set • Disabling the clock prevents flip-flops from transitioning and reduces test power in the CUT and in the clock tree

  8. Clock Scheme Modification

  9. Generating the test Clock Logic Power Savings Clock Power Savings

  10. Vector Filtering

  11. Single LFSR inhibition • Single LFSR inhibition means that only one subsequence has been inhibited in the experiments performed, in order to keep negligible the area overhead of the decoding logic.

  12. MultipleLFSR inhibition

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