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Designing Combinational Logic Circuits - Chapter 6

This chapter discusses the design of combinational logic circuits, including static CMOS circuit properties, transistor sizing, input pattern effects on delay, fan-in considerations, and design techniques for fast complex gates.

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Designing Combinational Logic Circuits - Chapter 6

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  1. Chapter 6 Designing CombinationalLogic Circuits November 2002.

  2. Combinational vs. Sequential Logic Combinational Sequential Output = ( ) f In, Previous In Output = ( ) f In

  3. At every point in time (except during the switching transients) each gate output is connected to either V or V via a low-resistive path. DD ss The outputs of the gates assumeat all timesthevalue of the Boolean function, implemented by the circuit (ignoring, once again, the transient effects during switching periods). This is in contrast to the dynamic circuit class, which relies on temporary storage of signal values on the capacitance of high impedance circuit nodes. Static CMOS Circuit

  4. Complementary CMOS Logic Style

  5. Static Complementary CMOS VDD In1 PMOS only In2 PUN … InN F(In1,In2,…InN) In1 In2 PDN … NMOS only InN PUN and PDN are dual logic networks

  6. NMOS Transistors in Series/Parallel Connection • Transistors can be thought as a switch controlled by its gate signal • NMOS switch closes when switch control input is high

  7. PMOS Transistors in Series/Parallel Connection

  8. Example Gate: NAND

  9. Example Gate: NOR

  10. B A C D Complex CMOS Gate OUT = D + A • (B + C) A D B C

  11. Constructing a Complex Gate

  12. CMOS Properties • Full rail-to-rail swing; high noise margins • Logic levels not dependent upon the relative device sizes; ratioless • Always a path to Vdd or Gnd in steady state; low output impedance • Extremely high input resistance; nearly zero steady-state input current • No direct path steady state between power and ground; no static power dissipation • Propagation delay function of load capacitance and resistance of transistors

  13. Properties of Complementary CMOS Gates Snapshot 1. High noise margins : V and V are at V and GND , respectively. OH OL DD 2. No static power consumption : There never exists a direct path between V and DD V ( GND ) in steady-state mode . SS 3. Comparable rise and fall times: (under appropriate sizing conditions)

  14. CL CL CL CL Threshold Drops VDD VDD PUN S D VDD D S 0 VDD 0 VDD - VTn VGS PDN VDD 0 VDD |VTp| VGS D S VDD S D

  15. Rp Rp Rp Rp Rp Rp A A A B B A Cint Rn CL CL CL Rn Rn Rn Rn B A B A A Cint Switch Delay Model Req A A NOR2 INV NAND2

  16. Rp Rp B A Cint CL Rn A Input Pattern Effects on Delay • Delay is dependent on the pattern of inputs • Low to high transition • Both inputs go low • Delay is 0.69 Rp/2 CL • One input goes low • Delay is 0.69 Rp CL • High to low transition? • Both inputs go high • Delay is 0.69 2Rn CL Rn B

  17. Delay Dependence on Input Patterns A=B=10 A=1 0, B=1 A=1, B=10 Voltage [V] time [ps] NMOS = 0.5m/0.25 m PMOS = 0.75m/0.25 m CL = 100 fF

  18. Rp Rp 2 2 Rp Rp B A B A Rn Cint Cint CL CL Rn Rn Rn B A B A 1 1 Transistor Sizing 4 4 2 2

  19. A D Transistor Sizing a Complex CMOS Gate B 8 6 4 3 C 8 6 4 6 OUT = D + A • (B + C) A 2 D 1 B 2 C 2

  20. D C B A C3 C2 C1 CL Fan-In Considerations A Distributed RC model (Elmore delay) tpHL = 0.69 Reqn(C1+2C2+3C3+4CL) Propagation delay deteriorates rapidly as a function of fan-in – quadratically in the worst case. B C D

  21. quadratic tpHL tp linear tp as a Function of Fan-In Gates with a fan-in greater than 4 should be avoided. tp (psec) tpLH fan-in

  22. tp as a Function of Fan-Out All gates have the same drive current. tpNOR2 tpNAND2 tpINV tp (psec) Slope is a function of “driving strength” eff. fan-out

  23. tp as a Function of Fan-In and Fan-Out • Fan-in: quadratic due to increasing resistance and capacitance • Fan-out: each additional fan-out gate adds two gate capacitances to CL tp = a1FI + a2FI2 + a3FO

  24. C3 C2 C1 CL Fast Complex Gates:Design Technique 1 • Transistor sizing • as long as fan-out capacitance dominates • Progressive sizing Distributed RC line M1 > M2 > M3 > … > MN (the fet closest to the output is the smallest) InN MN In3 M3 In2 M2 Can reduce delay by more than 20%; decreasing gains as technology shrinks In1 M1

  25. C2 C1 C1 C2 CL CL Fast Complex Gates:Design Technique 2 • Transistor ordering critical path critical path 01 charged charged 1 In1 In3 M3 M3 1 1 In2 In2 M2 discharged M2 charged 1 In3 discharged In1 charged M1 M1 01 delay determined by time to discharge CL, C1 and C2 delay determined by time to discharge CL

  26. Fast Complex Gates:Design Technique 3 • Alternative logic structures F = ABCDEFGH

  27. CL CL Fast Complex Gates:Design Technique 4 • Isolating fan-in from fan-out using buffer insertion

  28. Fast Complex Gates:Design Technique 5 • Reducing the voltage swing • linear reduction in delay • also reduces power consumption • But the following gate is much slower! • Or requires use of “sense amplifiers” on the receiving end to restore the signal level (memory design) tpHL = 0.69 (3/4 (CL VDD)/ IDSATn ) = 0.69 (3/4 (CL Vswing)/ IDSATn )

  29. Sizing Logic Paths for Speed • Frequently, input capacitance of a logic path is constrained • Logic also has to drive some capacitance • Example: ALU load in an Intel’s microprocessor is 0.5pF • How do we size the ALU datapath to achieve maximum speed? • We have already solved this for the inverter chain – can we generalize it for any type of logic?

  30. Buffer Example In Out CL 1 2 N (in units of tinv) For given N: Ci+1/Ci = Ci/Ci-1 To find N: Ci+1/Ci ~ 4 How to generalize this to any logic path?

  31. Logical Effort p – intrinsic delay (3kRunitCunitg) - gate parameter  f(W) g – logical effort (kRunitCunit) – gate parameter  f(W) f – effective fanout Normalize everything to an inverter: ginv =1, pinv = 1 Divide everything by tinv (everything is measured in unit delays tinv) Assume g = 1.

  32. Delay in a Logic Gate Gate delay: d = h + p effort delay intrinsic delay Effort delay: h = g f logical effort effective fanout = Cout/Cin Logical effort is a function of topology, independent of sizing Effective fanout (electrical effort) is a function of load/gate size

  33. Logical Effort • Inverter has the smallest logical effort and intrinsic delay of all static CMOS gates • Logical effort of a gate presents the ratio of its input capacitance to the inverter capacitance when sized to deliver the same current • Logical effort increases with the gate complexity

  34. Logical Effort Logical effort is the ratio of input capacitance of a gate to the input capacitance of an inverter with the same output current g = 5/3 g = 4/3 g = 1

  35. Logical Effort of Gates t pNAND g = p = d = t pINV Normalized delay (d) g = p = d = F(Fan-in) 1 2 3 4 5 6 7 Fan-out (h)

  36. Logical Effort of Gates t pNAND g = 4/3 p = 2 d = (4/3)h+2 t pINV Normalized delay (d) g = 1 p = 1 d = h+1 F(Fan-in) 1 2 3 4 5 6 7 Fan-out (h)

  37. Logical Effort of Gates

  38. Add Branching Effort Branching effort:

  39. Multistage Networks Stage effort: hi = gifi Path electrical effort: F = Cout/Cin Path logical effort: G = g1g2…gN Branching effort: B = b1b2…bN Path effort: H = GFB Path delay D = Sdi = Spi + Shi

  40. Optimum Effort per Stage When each stage bears the same effort: Stage efforts: g1f1 = g2f2 = … = gNfN Effective fanout of each stage: Minimum path delay

  41. Optimal Number of Stages For a given load, and given input capacitance of the first gate Find optimal number of stages and optimal sizing Substitute ‘best stage effort’

  42. Logical Effort From Sutherland, Sproull

  43. Example: Optimize Path g = 1f = a g = 1f = 5/c g = 5/3f = c/b g = 5/3f = b/a Effective fanout, F = G = H = h = a = b =

  44. Example: Optimize Path g = 1f = a g = 1f = 5/c g = 5/3f = c/b g = 5/3f = b/a Effective fanout, F = 5 G = 25/9 H = 125/9 = 13.9 h = 1.93 a = 1.93 b = ha/g2 = 2.23 c = hb/g3 = 5g4/f = 2.59

  45. Example: Optimize Path g4 = 1 g1 = 1 g2 = 5/3 g3 = 5/3 Effective fanout, H = 5 G = 25/9 F = 125/9 = 13.9 f = 1.93 a = 1.93 b = fa/g2 = 2.23 c = fb/g3 = 5g4/f = 2.59

  46. Example – 8-input AND

  47. Method of Logical Effort • Compute the path effort: F = GBH • Find the best number of stages N ~ log4F • Compute the stage effort f = F1/N • Sketch the path with this number of stages • Work either from either end, find sizes: Cin = Cout*g/f Reference: Sutherland, Sproull, Harris, “Logical Effort, Morgan-Kaufmann 1999.

  48. Summary Sutherland, Sproull Harris

  49. Pass-TransistorLogic

  50. Pass-Transistor Logic

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