정 용 군 ( 전자공학과 대학원 ) jdragon@trut.chungbuk.ac.kr 대상 : VLSI 설계 연구회 1,2,3 학년

1. Synopsys교육 1 Synopsys Tool 교육 정 용 군 (전자공학과 대학원) jdragon@trut.chungbuk.ac.kr 대상 : VLSI 설계 연구회 1,2,3 학년 기간 : 99.1.11 ~ 99.1.13

2. Synopsys 교육 1 Synopsys의 구조 Design Analyzer VHDL System DesignWare Simulation Develop HDL Compiler Family SGE HDL Synthesis TM TM HDL Compiler VHDL Compiler Verilog VHDL (verilog) Netlist Schematics Netlist Design Compiler Family State tables Schematics Circuit optimization State tables Goals TM TM Design Compiler FPGA Compiler (CMOS) Technology Test Compiler Family Test Library Vector TM TM Test Compiler Test Compiler Plus Library Compiler

3. Synopsys 교육 1 Synopsys 환경 설정 - 자신의 .cshrc 파일에 다음을 추가한다.(donald 기준) ################# setup for synopsys #################### setenv SYNOPSYS /tools/synopsys set path = ( $path $SYNOPSYS/sparcOS5/syn/bin ) set path = ( $path $SYNOPSYS/sparcOS5/sim/bin ) set path = ( $path $SYNOPSYS/sparcOS5/sge/bin ) set path = ( $path $SYNOPSYS/iview2/bin ) set path = ( $path /opt/SUNWspro/bin ) source $SYNOPSYS/admin/install/sim/environ.csh ######################################################

4. Synopsys 교육 1 VHDL System Simulator sge : Simulation Graphical Environment vhdlan : VHDL analyzer gvan : Graphical VHDL analyzer vhdlsim : VHDL simulator vhdldbx : VHDL debugger Synthesis with VHDL => Design Analyzer

5. Synopsys 교육 1 VHDL System Simulator 1. SGE 시작 Ex : [donald:home/grad/dragon]sge &

6. Synopsys 교육 1 2. Drawing circuits (Schematic editor)

7. Synopsys 교육 1 2.1. Drawing circuits (Schematic editor) (cont.) : Add / Symbol command Select components to place

8. Synopsys 교육 1 2.2. Drawing circuits (Schematic editor) (cont.) : Add / Wire command Draw the line to input/ output port of symbols

9. Synopsys 교육 1 2.3. Drawing circuits (Schematic editor) (cont.) : Add / Netname command => determine netname * If net is BUS, enter the net name ; A(3:0), B(4:0) etc. enter net name

10. Synopsys 교육 1 2.4. Drawing circuits (Schematic editor) (cont.) : Add / I/O Marker command => determine input/output

11. Synopsys 교육 1 2.5. Drawing circuits (Schematic editor) (cont.) : File / Save command => .sch, ._sc

12. Synopsys 교육 1 3. Compile circuits (Schematic editor) : Netlist => VHDL code 3.1. Creating a symbol automatically generated by Schematic editor If select this block, display information of designed circuits

13. Synopsys 교육 1 3.1.1. Creating a symbol (cont.) => To simulate and synthesis after transforming netlist to VHDL code => To edit symbol by designer => Must create a symbol for each schematic : .sym

14. Synopsys 교육 1 3.1.2. Creating a symbol (cont.) Draw / Rect => draw box

15. Synopsys 교육 1 3.1.3. Creating a symbol (cont.) Draw / Line => draw line Add / Pin => determine in/out port

16. Synopsys 교육 1 3.1.4. Creating a symbol (cont.) Add / Pin Attr => determine pin name and polarity pin name BUS => A(3:0), B(5:0) change polarity

17. Synopsys 교육 1 3.1.5. Creating a symbol (cont.) Add / Pin Name Loc determine position of pin name

18. Synopsys 교육 1 3.1.6. Creating a symbol (cont.) Add / Window Using the symbol created , is placed with this shape

19. Synopsys 교육 1 3.1.7. Creating a symbol (cont.)

20. Synopsys 교육 1 3.2. Generate VHDL code vi editor Netlist => VHDL code

21. Synopsys 교육 1 4. Simulation => It is the most useful method using test bench. 4.1 Test Bench Generation 1) automatic generation by SGE 2) code test bench for yourself

22. Synopsys 교육 1 4.1.1 Automatic generation by SGE

23. Synopsys 교육 1 4.1.1 Automatic generation by SGE (cont.) : Tools / Code VHDL Models => tb_(circuit-name).vhd generate test bench Test bench is automatically generated, but insert input signal to test bench with using editor program(vi)

24. Synopsys 교육 1 4.1.1 Automatic generation by SGE (cont.) : Tools / Analyze VHDL Models => compile test bench

25. Synopsys 교육 1 4.1.1 Automatic generation by SGE (cont.) : Tools / Start VHDL Simulator => compile test bench VHDL debugger (vhdldbx) WAVE

26. Synopsys 교육 1 4.1.2 Coding test bench for yourself input signal output signal Designed circuit structual description test bench

27. Synopsys 교육 1 Example of input signals for test bench clock of 250 ns period reset signal

28. Synopsys 교육 1 4.2 Simulation < Flow > error vhdl source test bench vhdlan vhdldbx wave OK error

29. Synopsys 교육 1 4.2.1 vhdlan (shell mode) usage : vhdlan [option] (vhdl source, test bench) [option] -l : read vhdl file and generate *.lis file having error message -c : generate object code compiled -v : display information of analyzer Ex : vhdlan -l -c test.vhd cf) graphic mode : gvan

30. Synopsys 교육 1 4.2.2 vhdldbx ( ex : [donald:home/grad/dragon/WORK]vhdldbx & ) select configuration edit *.log file : have information in/out port being displayed in wave window ex) vi test.log trace clk trace a[0] . . 1. include *.log 2. run 25000

31. Synopsys 교육 1 4.2.3 wave ( ex : [donald:home/grad/dragon/WORK]waves & ) waveform file *.ow

32. Synopsys 교육 1 4.2.3 wave ( ex : [donald:home/grad/dragon/WORK]waves & ) (cont.)

33. Synopsys 교육 1 Synthesis with VHDL Inputs and Outputs of Design Compiler ` Design Optimized design Design Compiler Operating Environment Description Reports Schematics Timing, Area and Design Rule Goals

34. Synopsys 교육 1 Design Compiler Interaction design_analyzer (graphical mode) Menu dc_shell (shell mode) Design Compiler command line

35. Synopsys 교육 1 Design analyzer 실행 Ex : [donald:home/grad/dragon]design_analyzer &

36. Synopsys 교육 1 File / Read command => To read designs into Design Compiler Read formats; DB EDIF Equation LSI Mentor PLA State table Tegas Verilog VHDL

37. Synopsys 교육 1 File / Analyzecommand => syntax checks VHDL code, .syn and .mra file 생성 vhdl source file find file to analyze determine format to analyze Library is the name of working directory.

38. Synopsys 교육 1 File / Elaboratecommand => elaborate after analyze to bring design into Design Compiler memory select working directory name * If you change VHDL code, analyze and elaborate again automatically re-analyzes out of date intermediate files if source can be found

39. Synopsys 교육 1 Analysis / Link Designcommand => To ensure all sub-elements of your hierarchical designs are available.

40. Synopsys 교육 1 Analysis / Check Designcommand => execute check design before you optimize your design

41. Synopsys 교육 1 Attributes / Clockcommand

42. Synopsys 교육 1 Design Optimization 1. Constraints

43. Synopsys 교육 1 2. Design optimization => type of CLB and IOB of Xilinx

44. Synopsys 교육 1 FPGA