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Nanoscale structures in Integrated Circuits

Nanoscale structures in Integrated Circuits. By Edward Mulimba. Presentation Outline . Introduction and history Review of current chip manufacturing methods Limitations of current methods 2 currently researched methods conclusion. Nanotech Definition.

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Nanoscale structures in Integrated Circuits

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  1. Nanoscale structures in Integrated Circuits By Edward Mulimba

  2. Presentation Outline • Introduction and history • Review of current chip manufacturing methods • Limitations of current methods • 2 currently researched methods • conclusion

  3. Nanotech Definition • Creation and use of materials, systems or components involving measurements between 1 and 100 nm • nanometer = one billionth of a meter (10 –9 meter ) • Herald new advances in engineering, medicine, and computing • Spending US ($3.7 billion) Japan ($1 billion) and EU($3.3 billion)

  4. What is Integrated Circuit? • Small electronic device made from semiconductor material (usually silicon) • Developed mainly by Jack Kilby of Texas Instruments • Usually contains transistors and other small components

  5. Moore’s Law • Intel co founder Gordon Moore observed in 1965 • Number of transistors per integrated circuit chip would double in each technology generation • Early generation just had 30 transistors, today could exceed few hundred million per chip.

  6. Table showing transistor size trend Source ITRS Executive Summary 2003 Edition

  7. Current basic chip fabrication method LIGHT MASK PHOTORESIST FILM SUBSTRATE

  8. Current lithography techniques • Extreme ultraviolet (EUV) lithography • Most prominent • Backed by Intel, Motorola, and now IBM • Uses very short wavelength

  9. Current lithography techniques (cont) • Electron-beam lithography • Backed by Lucent Technology, Nikon • Uses electrons instead of light • Takes too long to make chip

  10. Current lithography techniques (cont) • Maskless lithography • Developed jointly by Swedish and Dutch companies • Uses millions of microscopic mirrors to direct laser light on wafer • Too slow and costly

  11. Limitations of current chip fabrication methods • Cost of fabrication plants is exorbitant • Moore’s second law – corollary to first “The cost of new chip fabrication plants increases exponentially as new features get smaller” • Wires carved on silicon by standard lithography methods generate too much heat

  12. Limitations of current chip fabrication methods (cont). • Physical limitations for example transistors at about 50 nanometers dimensions electrons start obeying quantum laws

  13. Advantages of molecular chip making • Could be relatively easier to make • Potentially cost less than current methods • Molecules can be used to build items that are few nanometers in size • Lack imperfections that arise from etching lines as done in lithography

  14. IBM molecular IC • Uses carbon nanotubes which can be grown into smaller dimensions • Instead of constructing good nanotubes one by one, many are built then defective ones are destroyed on the wafer • Patented method referred to “constructive destruction” • IBM to conduct more research to see if carbon nanotubes outperform silicon transistors

  15. Using germs to build circuits • Research carried out at University of Texas lead by A. Belcher • Hired virus to be a nano-construction worker • Genetically engineered viruses grab dots of zinc sulfide to form viral semiconductors • They are then arranged into highly ordered structures which could be made into nanoscale devices.

  16. Research Progress • The researchers have been able to form nanometer scale semiconductor crystals using these viruses (2-3 nm crystals) • Application of this kind of technology would be sensors, quantum-dot flash memories • Goal is to tinker with viral DNA so as to create desired semiconductor components with the immediate target being a transistor.

  17. Recap • Use of current technology can extend Moore’s Law for few years. • New methods such as discussed in the presentation may offer a cheaper and effective way of extending the law in the long term • Challenge for computer scientists to design systems that can fully utilize the changing integrated circuits

  18. Questions?

  19. References • Fairley, P. Germs that build Circuits. IEEE Spectrum Nov. 2003 pg 37 • Savage, N. A revolutionary Chipmaking Technique. IEEE Spectrum Nov. 2003 pg 18 • International Technology Roadmap for Semiconductors. Executive Summary 2003 • Rotman, D. Molecular computing. Technology Review. May 2000 v103 • Service, R. Assembling nanocircuits from Bottom up. Science August 2001 v293

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