Address Decoding for Memory and I/O - PowerPoint PPT Presentation

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Address Decoding for Memory and I/O

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  1. Address Decoding for Memory and I/O Lecture 3 - Instruction Set - Al

  2. Address Decoding • Address Decoding Designs • Full Address Decoding • Partial Address Decoding • Block Address Decoding • Implementation • Random, Decoders, PROM, FPGA Lecture 3 - Instruction Set - Al

  3. Address Decoding • Required for a microcomputer where memory and I/O support are essential • Needed for embedded system when on chip microcontroller memory is not sufficient Lecture 3 - Instruction Set - Al

  4. The Memory Space • 2 basic approaches • Memory mapped system – main memory and I/O space are just different addresses or regions – or memory mapped I/O (MMIO) • Addressing is the same pins for memory and I/O • Advantage – less pin and hardware complexity • Port Mapped I/O – have unique pins (signals) that differentiate memory and I/O address spaces • Advantage – If limited memory, memory is memory • Advantage – Large I/O space Lecture 3 - Instruction Set - Al

  5. Other architectures • Harvard Architecture • Separate memory spaces for instructions and data • Requires pin(s) to differentiate • I/O is MMIO (also have PMIO) • Check these out on www.wikipedia.com Lecture 3 - Instruction Set - Al

  6. The 68000 Memory Space • 23 address lines • 223 words with UDS* and LDS* • This is 8M words or 16M bytes Lecture 3 - Instruction Set - Al

  7. Address Map • When implementing a system the designer creates a memory map. • Map would include where RAM, ROM and I/O are. Lecture 3 - Instruction Set - Al

  8. Full address decoding • Each addressable location within the memory components responds to only a single unique address. Lecture 3 - Instruction Set - Al

  9. Example of full address decoding Lecture 3 - Instruction Set - Al

  10. Ex continued Lecture 3 - Instruction Set - Al

  11. Partial Address Decoding • Some of address lines are unused • Least complex and most inexpensive • Each component will actually respond to several addresses Lecture 3 - Instruction Set - Al

  12. Partial Address decoding example Lecture 3 - Instruction Set - Al

  13. Block Address decoding • Compromise between full and partial. • Don’t decode all of address lines but do decode more than the bare minimum. • Less repeated addresses for each populated device Lecture 3 - Instruction Set - Al

  14. Designing the decode logic • Multiple methods of implementing the decode logic • One method is of course to implement it with “random logic” – i.e., AND gates, OR gates, inverters, NAND gates, NOR gates • Advantage – speed • Disadvantage – possibly the number of chips Lecture 3 - Instruction Set - Al

  15. Decoders • USE m-line-to-n-line decoders • Decode an m-bit input into one of n outputs where n = 2m • Popular 74LS138 – 3-to-8 decoder • Another 74LS154 – 4-to-16 decoder Lecture 3 - Instruction Set - Al

  16. Decoder Truth table Lecture 3 - Instruction Set - Al

  17. Example of decoder use Lecture 3 - Instruction Set - Al

  18. Implementation Lecture 3 - Instruction Set - Al

  19. PROMS • A PROM can also be use to implement logic functions • Can use it to do address decoding Lecture 3 - Instruction Set - Al

  20. Example of PROM use • Decoder design must be cheap and versitle. Lecture 3 - Instruction Set - Al

  21. PROM Programming Lecture 3 - Instruction Set - Al

  22. PROM System • Advantage- • Ability to select blocks of differing size • Versitility Lecture 3 - Instruction Set - Al

  23. FPGA, PLA, PAL • Programmable Logic Arrays • AND plane – OR plane • Programmable Array Logic • Limited PLA • FPGA – A network of CLBs Lecture 3 - Instruction Set - Al

  24. PAL vs PLA • In a PAL the ouput’s connection to product terms is fixed • More limited logic equation support Lecture 3 - Instruction Set - Al

  25. Special devices • There are also special chips specifically designed for address decoding • Some may be designed for a specific family of chips Lecture 3 - Instruction Set - Al