Ways to design a processor

1. Ways to design a processor • Random logic • Micro-programmed control units. • Reduced Instruction Set Computers. • Pipelined design

2. CISC • Virtually from the start of the microprocessor era until the 1980's, all microprocessor design was driven using a common fundamental architecture nowadays referred to as CISC or Complex Instruction Set Computer. • A complex instruction set computer is a computer where single instructions can perform numerous low-level operations like a load from memory, an arithmetic operation, and a memory store as its name proposes “Complex Instruction Set ”.

3. CISC • The emergence and domination of the CISC architecture was motivated by two main characteristics that processors had to support given the historical technological constraints: • The instruction set had to be simple to use for the assembly programmer • Memory access had to be kept to a minimum

4. CISC • The solution devised to answer this, was to hardwire basic instructions, and use microcode internal to the processor to interface these instructions.   • This way, each instruction of the processor's instruction set could be mapped inside the processor to a series of microcode instructions that would carry it out. • This enables CISC instruction set to be rich and complex, where a single assembly language instruction can be mapped to numerous microcode instruction, providing for a higher-level abstraction for the assembly language programmer, and compact instruction packaging reducing memory accesses.

5. CISC • CISC has the capacity to perform multi-step operations or addressing modes within one instruction set.  Example • MULT RegA, RegB

6. CISC Key features • Large instruction sets • More addressing modes • Uses instruction of variable size • Instruction have different fetching time • Instruction set is large and simple • Hardware implementations of HLL statements • e.g. CASE (switch) on VAX

7. Intention of CISC • Ease compiler writing • Improve execution efficiency • Complex operations in microcode • Support more complex HLLs

8. What is RISC? • A reduced instruction set computer is a computer which only uses simple commands that can be divided into several instructions which achieve low-level operation within a single CLK cycle, as its name proposes “Reduced Instruction Set”.

9. What is RISC? • This is small or reduced set of instructions. Here, every instruction is expected to attain very small jobs. • In this machine, the instruction sets are modest and simple, which help in comprising more complex commands. • Each instruction is of the similar length; these are wound together to get compound tasks done in a single operation. • Most commands are completed in one machine cycle. This pipelining is a crucial technique used to speed up RISC machines.

11. Reduced Instruction Set Computers • Example : • LOAD A, 1:3 • LOAD B, 4:2 • PROD A, B • STORE 1:3, A

12. Reduced Instruction Set Computers • {Make hardware Simpler, but quicker} • Key features • Large number of general purpose registers • Use of compiler technology to optimize register use • Limited and simple instruction set • Emphasis on optimising the instruction pipeline • One machine cycle instructions • Same length instructions

13. RISC • Because most RISC instruction are the same length and execute in one machine cycle, these can be fetched with only one access to memory and executed in parallel, where multiple execution units inside the processor work concurrently on different instructions (a superscalar architecture).   • Also the RISC architecture naturally lends itself to the implementation of effective instruction pipelines.   • Using a pipeline, instructions can start executing before previous ones have completed. • That is, at the same time an instruction is executed, another is decoded while still another is fetched.

14. CISC VS RISC •  In CISC machines pipelining is less effective as the variation in length of the CISC instructions cause the instruction pipeline to stall when it encounters instructions of various lengths. • Hence using the RISC architecture provides for effective pipelines compared to CISC.

15. CISC VS RISC • On the other hand, because in most cases many RISC instructions are needed to perform the same functionality as a CISC instruction, RISC programs have greater memory requirements.   • Hence RISC computer will generally be equipped with more memory and cache memory than their CISC counterparts.   • Also the performance of a RISC machine is more dependent on the quality of the compiler generated code it executes than CISC machines.

16. Implications RISC • Best support is given by optimising most used and most time consuming features • Large number of registers • Operand referencing • Careful design of pipelines • Branch prediction etc. • Simplified (reduced) instruction set

17. RISC Characteristics • One instruction per cycle • Register to register operations • Few, simple addressing modes • Few, simple instruction formats • Hardwired design (no microcode) • Fixed instruction format • More compile time/effort

18. CISC VS RISC

19. CISC VS RISC

20. CISC VS RISC

21. Comparison of processors • CISCRISCSuperscalar • IBM DEC VAX Intel Motorola MIPS IBM Intel • 370/168 11/780 486 88000 R4000 RS/6000 80960 • 1973 1978 1989 1988 1991 1990 1989 • No. of instruction • 208 303 235 51 94 184 62 • Instruction size (octets) • 2-6 2-57 1-11 4 32 4 4 or 8 • Addressing modes • 4 22 11 3 1 2 11 • GP Registers • 16 16 8 32 32 32 23-256 • Control memory (k bytes) (microprogramming) • 420 480 246 0 0 0 0