SYNTHESIS Issues in synthesizable VHDL descriptions (from VHDL Answers to FAQ by Ben Cohen)
Synthesis Sensitivity Rules for Processes • If the synthesized process has a static sensitivity list, then every read signal must be a member of this list. • Otherwise the synthesis tool will create a hardware configuration that concurs with this requirement
Synthesized Hardware for Arrays, Signals and Variables • Arrays : defines vectors • Represent either the output of CL, or a register or a latch. • Rules for Signals and Variables in clocked processes or equivalent clocked process ( wait unitil Clk=‘1’; or if(Clk’event and Clk=‘1’ then …, or Sig <= not In1 When Clk’event and Clk=‘1’) • Signals represent registers • Reading a variable before assigning a value to that variable implies “reading old values of that variable”, or a register implementation for that variable.
Signals and Variables • Rules in non-clocked processes : • A latch is inferred for signals or variables when one of the following conditions occurs (otherwise, the objects represents a bus output of combinational logic) • The signal or variable is in an equivalent process where not all the alternatives of a conditional expression are considered • The VHDL attribute ‘event is not present in the conditional expression. • The variable is read in any path prior to being assigned a value.
Signals and Variables • One dimensional array declarations and Synthesis implications
Signals and Variables • One-dimensional array declarations with variables
Synchronous reset and Asynchronous reset • Synchronous Reset
Synchronous reset and Asynchronous reset • Asynchronous Reset
Avoid the partial asynchronous reset! • Avoid the partial asynchronous reset of implied registers in a clocked process • If asynchronous reset is required, either reset ALL the implied registers, or use multiple clocked processes.
Latch inference in functions? • Since variables declared in a function do not retain their values between calls to this function, latches will not be inferred by synthesis. • Even if the latching criteria are satisfied. • To avoid any confusion, the function should be writeen in a non-latching coding style. To agreewith the basic VHDL synthesis coding style.
Variable initialization and Lifetime • Variables are initialized when, and only when, its declaration is elaborated. • Concurrent procedure is equivalent to a process. Its sensitivity list is extracted from all the actual signals whose mode is in or inout. • In synthesis, DO NOT initialize variables in the declaration statements of the variables. • Instead, declare the variable UNINITIALIZED, and in the body of the process or subprogram, write an initialization statement(e.g. My_variable := 0; ) • In synthesis, DO NOT declare constants that are initialized to values of formal parameters or ports.
Variable initialization – not synthesizable • Non-synthesizable VHDL code
Variable initialization – not synthesizable • Synthesizable VHDL code
Wait statement • A process with a sensitivity list cannot contain any explit ‘wait’ statement, any called procedure from such a process cannot contain a ‘wait’ statement. • ‘wait’ statement can be used anywhere in a process except in a ‘for … loop’ statement or in a subprogram. • In most synthesizers, there can only be a sinlge ‘wait’ statement in a process. Allowing a ‘wait’ statement in a subprogram would imply multiple ‘wait’ statements, if that subprogram is called multiple times from within a process. • If a subprogram is called as a concurrent procedure, then there is an implied wait statement at the end of that procedure. Adding a ‘wait’ would then include two ‘wait’ statements. • Multiple ‘wait’ statements are allowed in behavioral synthesis.
Defining Shift Registers in Synthesis • Given the following code, synopsys tool yields an elaborate Error “Tried to use a synchronized value.” Where is the error ?
Defining Shift Registers in Synthesis • Several Code Errors of the Code <Figure 7.7> • Data should NOT be in the sensitivity list. • Variable Reg implies a register (the variable reads on old value) • Temp is out of (clk’event …) and cannot be assigned with ‘synchronized variables’.
Defining Shift Registers in Synthesis • Corrected Shift Register Model 1 (Reg – becomes a signal)
Defining Shift Registers in Synthesis • Improved Shift Register Model (concatenation operator is used)
Register File • n words deep by m bit wide register file • Multi-dim arrays: • not allowed in synthesis for signals or variable objects • allowed as constants or table lookups. • User-defined Register File • Use two one-dim. Array types • Figure 7.8 • Use high-level parameterized components like RAM, Counters, adders, multipliers, FIFOs, LESRs, pipeline registers multipliers, if they are available
MUX • Using concurrent signal assignment
DeMUX • Using concurrent signal assignment
DeMUX • Using a process
DeMUX • Using a process, no loop
Barrel Shifter • Barrel Shifter
Barrel Shifter • Non-Synthesizable Barrel Shifter
Barrel Shifter • Synthesis problems • The Slice “D_in((D_in’left – Amount) downto 0) & …” is non-compatable (Amount is a dynamic value) • The vector “D_in(D_in’left downto (D_in’left – Amount + 1))” is a null array when amount is zero.
Barrel Shifter • Synthesizable model: the loop counter is compared against the input Amount.
Barrel Shifter • Synthesizable model: case statement & process
Use of “don’t care” in case statement • In VHDL, “don’t care” means a ‘-’ state, not ‘u’ or ‘1’ or anything else • Maybe useful during simulation to ensure that a signal is not resolved with any other signal.
Use of “don’t care” in case statement • std_logic 9 values • In synthesis, the “don’t care” – should be used in assignments only, not in expressions to be used for comparisons.
Use of “don’t care” in case statement • Case statement with No “Don’t Care” – covers all conditions
Use of “don’t care” in case statement • Nested case statement
Use of “don’t care” in case statement • Using Type unsigned and To_Integer( )
IF statement • IF statement(instead of Don’t care) • Shorter code, Higher priority signal – near the top of the if construct. • Synopsys will place those signals closer to the output than signals used in the expression occurring later on.