1 / 24

Integrated RF Receivers

Integrated RF Receivers. Design Issues. Presented by: Sameh Assem Ibrahim. Outline. RF Receiver Architectures The Proposed Architecture Image Rejection Sensitivity to Process Variations References. RF Receiver Architectures. Super-Heterodyne Receiver. RF Receiver Architectures.

tiger-cunningham
Télécharger la présentation

Integrated RF Receivers

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. Integrated RF Receivers Design Issues Presented by: Sameh Assem Ibrahim

  2. Outline • RF Receiver Architectures • The Proposed Architecture • Image Rejection • Sensitivity to Process Variations • References

  3. RF Receiver Architectures

  4. Super-Heterodyne Receiver RF Receiver Architectures Block Diagram

  5. Super-Heterodyne Receiver • High selectivity •  High sensitivity • Most widely used in discrete implementations • Difficult to integrate • Very high Q filters are required RF Receiver Architectures Advantages and Disadvantages

  6. Homodyne Receiver RF Receiver Architectures Block Diagram

  7. Homodyne Receiver • High integratability • No need for high image rejection ratios • DC offsets • Back radiation • High flicker noise • Need for high I-Q matching accuracy RF Receiver Architectures Advantages and Disadvantages

  8. Low-IF Receiver RF Receiver Architectures Block Diagram

  9. Low-IF Receiver •  High integratability • No DC offset problems • No flicker noise • The best candidate for modern integrated receivers • Need for high I-Q matching accuracy RF Receiver Architectures Advantages and Disadvantages

  10. Image Rejection

  11. I PP PPF PPF flo1+flo2 frf fimage LNA fif fif flo1+flo2 frf fimage Q fif fif Notch Filter PP PP Image-reject PLL LO Divider The Choice of IF frf fif=frf-(flo1+flo2) fimage=2(flo1+flo2)-frf flo1 flo2 Image Rejection Precaution 1

  12. -frf -fim fim frf fLO -fLO f f The Use of Polyphase Filters Real Signals: -fif fif f Image Rejection Precaution 2

  13. -frf -fim fim frf f The Use of Polyphase Filters Complex Signals: -fLO f -fif fif f Image Rejection Precaution 2

  14. The Use of Polyphase Filters -fif fif -fif fif f f • Passive Polyphase Filter • Bandstop filter • Preferred at high frequencies • Active Polyphase Filter • Bandpass filter • Preferred at low frequencies • Can be used for channel selection Image Rejection Precaution 2

  15. I PP PPF PPF LNA Q Notch Filter PP PP Image-reject PLL LO Divider The Use of Polyphase Filters Passive Active Image Rejection Precaution 2

  16. LNA with a Notch Filter [6] Image Rejection Precaution 3

  17. Sensitivity to Process Variations

  18. The Use of Polyphase Filters Sensitivity analysis for passive polyphase filters [9] Sensitivity to Process Variations Precaution 1

  19. The Use of Polyphase Filters Sensitivity analysis for active polyphase filters Sensitivity to Process Variations Precaution 1

  20. I PP PPF PPF LNA Q Notch Filter PP PP Image-reject PLL LO Divider The Use of Polyphase Quadrature Generators Sensitivity to Process Variations Precaution 2

  21. The Use of Polyphase Quadrature Generators Sensitivity analysis for polyphase quadrature generators [9] Sensitivity to Process Variations Precaution 2

  22. I PP PPF PPF LNA Q Notch Filter PP PP Image-reject PLL LO Divider The Use of Double Quadrature Down Conversion (DQDC) [7] Sensitivity to Process Variations Precaution 3

  23. The Use of Double Quadrature Down Conversion (DQDC) [7] • SQDC • More affected by quadrature inaccuracy • DQDC • Less affected by quadrature inaccuracy Example: to reach 60 dB IRR 3% quadrature accuracy is enough for DQDC whereas 0.1 % is required for SQDC Sensitivity to Process Variations Precaution 3

  24. References • 1. A. A. Abidi, "Direct conversion radio transceivers for digital communications," IEEE J. Solid-State Circuits, vol. 30, pp. 1399-1410, Dec. 1995. • 2. J. Crols and M. Steyaert, "A single-chip 900-MHz CMOS receiver front-end with a high-performance low-IF topology," IEEE J. Solid-State Circuits, vol. 32, pp. 1935-1950, Dec. 1997. • 3. S. Jantzi and Adel S. Sedra, " Quadrature bandpass ΔΣ modulation for digital radio," IEEE J. Solid-State Circuits, vol. 30, pp. 1483-1492, Dec. 1995. • 4. J. Rudell and P. Gray, "A 1.9-GHz wide-band IF double conversion CMOS receiver for cordless telephone applications," IEEE J. Solid-State Circuits, vol. 32, pp. 2071-2088, Dec. 1997. • 5. S. Tadjpour and A. Abidi, "A 900 MHz dual conversion low-IF GSM receiver in 0.35 µm CMOS," IEEE J. Solid-State Circuits, vol. 36, pp. 1992-2002, Dec. 2001. • 6. H. Rategh and T. Lee, " 5-GHz CMOS wireless LANs," IEEE Transactions on Microwave Theory and Techniques, vol. 50, pp. 268-280, Jan. 2002. • 7. F. Behbahani and A. Abidi, "CMOS mixers and polyphase filters for large image rejection," IEEE J. Solid-State Circuits, vol. 36, pp. 873-887, June 2001. • 8. J. Crols and M. Steyaert, “ CMOS wireless transceiver design”, Kluwer Academic Publishers, 1997 • 9. S. Galal, “A new front-end architecture for RF single chip communication transcievers”, a thesis for masters degree, 1999

More Related