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ELEN 350 Single Cycle Datapath

ELEN 350 Single Cycle Datapath. Adapted from the lecture notes of John Kubiatowicz(UCB) and Hank Walker (TAMU). CPI. Inst. Count. Cycle Time. The Big Picture: The Performance Perspective. Performance of a machine is determined by: Instruction count Clock cycle time

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ELEN 350 Single Cycle Datapath

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  1. ELEN 350 Single Cycle Datapath Adapted from the lecture notes of John Kubiatowicz(UCB) and Hank Walker (TAMU)

  2. CPI Inst. Count Cycle Time The Big Picture: The Performance Perspective • Performance of a machine is determined by: • Instruction count • Clock cycle time • Clock cycles per instruction • Processor design (datapath and control) will determine: • Clock cycle time • Clock cycles per instruction • Single cycle processor: • Advantage: One clock cycle per instruction • Disadvantage: long cycle time

  3. How to Design a Processor: step-by-step • 1. Analyze instruction set => datapath requirements • the meaning of each instruction is given by the register transfers • datapath must include storage element for ISA registers • possibly more • datapath must support each register transfer • 2. Select set of datapath components and establish clocking methodology • 3. Assemble datapath meeting the requirements • 4. Analyze implementation of each instruction to determine setting of control points that effects the register transfer. • 5. Assemble the control logic

  4. 31 26 21 16 11 6 0 op rs rt rd shamt funct 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits 31 26 21 16 0 immediate op rs rt 6 bits 5 bits 5 bits 16 bits 31 26 0 op target address 6 bits 26 bits The MIPS Instruction Formats • All MIPS instructions are 32 bits long. The three instruction formats: • R-type • I-type • J-type • The different fields are: • op: operation of the instruction • rs, rt, rd: the source and destination register specifiers • shamt: shift amount • funct: selects the variant of the operation in the “op” field • address / immediate: address offset or immediate value • target address: target address of the jump instruction

  5. 31 26 21 16 11 6 0 op rs rt rd shamt funct 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits 31 26 21 16 0 op rs rt immediate 6 bits 5 bits 5 bits 16 bits 31 26 21 16 0 op rs rt immediate 6 bits 5 bits 5 bits 16 bits 31 26 21 16 0 op rs rt immediate 6 bits 5 bits 5 bits 16 bits Step 1a: The MIPS-lite Subset • ADD and SUB • addu rd, rs, rt • subu rd, rs, rt • OR Immediate: • ori rt, rs, imm16 • LOAD and STORE Word • lw rt, rs, imm16 • sw rt, rs, imm16 • BRANCH: • beq rs, rt, imm16

  6. Logical Register Transfers • RTL gives the meaning of the instructions • All start by fetching the instruction op | rs | rt | rd | shamt | funct = MEM[ PC ] op | rs | rt | Imm16 = MEM[ PC ] inst Register Transfers addu R[rd] <– R[rs] + R[rt]; PC <– PC + 4 subu R[rd] <– R[rs] – R[rt]; PC <– PC + 4 ori R[rt] <– R[rs] | zero_ext(Imm16); PC <– PC + 4 lw R[rt] <– MEM[ R[rs] + sign_ext(Imm16)]; PC <– PC + 4 sw MEM[ R[rs] + sign_ext(Imm16) ] <– R[rt]; PC <– PC + 4 beq if ( R[rs] == R[rt] ) then PC <– PC + 4 + sign_ext(Imm16)] || 00 else PC <– PC + 4

  7. Step 1: Requirements of the Instruction Set • Memory • instruction & data • Registers (32 x 32) • read RS • read RT • Write RT or RD • PC • Extender • Add and Sub register or extended immediate • Add 4 or extended immediate to PC

  8. Step 2: Components of the Datapath • Combinational Elements • Storage Elements • Clocking methodology

  9. Combinational Logic Elements (Basic Building Blocks) CarryIn A 32 • Adder • MUX • ALU Sum Adder 32 B Carry 32 Select A 32 Y MUX 32 B 32 OP A 32 Result ALU 32 B 32

  10. Verilog Implementation of Basic Blocks module adder(sum, carry_out, a, b, carry_in); input [31:0] a, b; input carry_in; output [31:0] sum; output carry_out; assign {carry_out, sum} = a+b; endmodule module mux(y, a, b, select); input [31:0] a, b; input select; output [31:0] y; assign y = (select) ? a: b; endmodule

  11. Storage Element: Register (Basic Building Block) Write Enable • Register • Similar to the D Flip Flop except • 32-bit input and output • Write Enable input • Write Enable: • negated (0): Data Out will not change • asserted (1): Data Out will become Data In Data In Data Out 32 32 Clk

  12. Verilog Implementation of Basic Blocks module register(data_out, clk, data_in, write_en); input [31:0] data_in; input clk, write_en; output [31:0] data_out; reg [31:0] data_out; always @(posedge clk) begin if (write_en) data_out = data_in; end endmodule

  13. Storage Element: Register File RW RA RB Write Enable 5 5 5 • Register File consists of 32 registers: • Two 32-bit output busses: busA and busB • One 32-bit input bus: busW • Register is selected by: • RA (number) selects the register to put on busA (data) • RB (number) selects the register to put on busB (data) • RW (number) selects the register to be writtenvia busW (data) when Write Enable is 1 • Clock input (CLK) • The CLK input is a factor ONLY during write operation • During read operation, behaves as a combinational logic block: • RA or RB valid => busA or busB valid after “access time.” busA busW 32 32 32-bit Registers 32 busB Clk 32

  14. Storage Element: Idealized Memory Write Enable Address • Memory (idealized) • One input bus: Data In • One output bus: Data Out • Memory word is selected by: • Address selects the word to put on Data Out • Write Enable = 1: address selects the memoryword to be written via the Data In bus • Clock input (CLK) • The CLK input is a factor ONLY during write operation • During read operation, behaves as a combinational logic block: • Address valid => Data Out valid after “access time.” Data In DataOut 32 32 Clk

  15. Clocking Methodology (Simple View) Clk • All storage elements are clocked by the same clock edge • CLK-to-Q + Longest Delay Path < Cycle Time • What is the longest path? . . . . . . . . . . . .

  16. Step 3: Assemble Datapath meeting our requirements • Register Transfer Requirements Datapath Assembly • Instruction Fetch • Read Operands and Execute Operation

  17. Next Address Logic Address Instruction Memory 3a: Overview of the Instruction Fetch Unit • The common RTL operations • Fetch the Instruction: mem[PC] • Update the program counter: • Sequential Code: PC <- PC + 4 • Branch and Jump: PC <- “something else” Clk PC Instruction Word 32

  18. 31 26 21 16 11 6 0 op rs rt rd shamt funct 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits 3b: Add & Subtract • R[rd] <- R[rs] op R[rt] Example: addu rd, rs, rt • Ra, Rb, and Rw come from instruction’s rs, rt, and rd fields • ALUctr and RegWr: control logic after decoding the instruction Rd Rs Rt ALUctr RegWr 5 5 5 busA Rw Ra Rb busW 32 Result 32 32-bit Registers ALU 32 32 busB Clk 32

  19. Register-Register Timing: One complete cycle Clk Clk-to-Q Old Value New Value PC Instruction Memory Access Time Rs, Rt, Rd, Op, Func Old Value New Value Delay through Control Logic ALUctr Old Value New Value RegWr Old Value New Value Register File Access Time busA, B Old Value New Value ALU Delay busW Old Value New Value Rd Rs Rt ALUctr Register Write Occurs Here RegWr 5 5 5 busA Rw Ra Rb busW 32 Result 32 32-bit Registers ALU 32 32 busB Clk 32

  20. 11 31 26 21 16 0 op rs rt immediate 6 bits 5 bits 5 bits 16 bits rd? 31 16 15 0 immediate 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 bits 16 bits Rd Rt RegDst Mux 3c: Logical Operations with Immediate • R[rt] <- R[rs] op ZeroExt[imm16] ] Rt? Rs ALUctr RegWr 5 5 5 busA Rw Ra Rb busW 32 Result 32 32-bit Registers ALU 32 32 busB Clk 32 Mux ZeroExt imm16 32 16 ALUSrc

  21. 11 31 26 21 16 0 op rs rt immediate 6 bits 5 bits 5 bits 16 bits rd 3d: Load Operations • R[rt] <- Mem[R[rs] + SignExt[imm16]] Example: lw rt, rs, imm16 Rd Rt RegDst Mux Rt? Rs ALUctr RegWr 5 5 5 busA W_Src Rw Ra Rb busW 32 32 32-bit Registers ALU 32 32 busB Clk MemWr 32 Mux Mux WrEn Adr Data In 32 ?? Data Memory Extender 32 imm16 32 16 Clk ALUSrc ExtOp

  22. 31 26 21 16 0 op rs rt immediate 6 bits 5 bits 5 bits 16 bits 3e: Store Operations • Mem[ R[rs] + SignExt[imm16] <- R[rt] ] Example: sw rt, rs, imm16 Rd Rt ALUctr MemWr W_Src RegDst Mux Rs Rt RegWr 5 5 5 busA Rw Ra Rb busW 32 32 32-bit Registers ALU 32 32 busB Clk 32 Mux Mux WrEn Adr Data In 32 32 Data Memory Extender imm16 32 16 Clk ALUSrc ExtOp

  23. 31 26 21 16 0 op rs rt immediate 6 bits 5 bits 5 bits 16 bits 3f: The Branch Instruction • beq rs, rt, imm16 • mem[PC] Fetch the instruction from memory • Equal <- R[rs] == R[rt] Calculate the branch condition • if (Equal) Calculate the next instruction’s address • PC <- PC + 4 + ( SignExt(imm16) x 4 ) • else • PC <- PC + 4

  24. 31 26 21 16 0 op rs rt immediate 6 bits 5 bits 5 bits 16 bits 4 Adder Mux Adder Datapath for Branch Operations • beq rs, rt, imm16 Datapath generates condition (equal) Inst Address Cond nPC_sel Rs Rt RegWr 5 5 5 busA 32 Rw Ra Rb 00 busW 32 32 32-bit Registers Equal? PC busB Clk 32 imm16 PC Ext Clk

  25. Inst Memory Adr Adder Mux Adder Putting it All Together: A Single Cycle Datapath Instruction<31:0> <21:25> <16:20> <11:15> <0:15> Rs Rt Rd Imm16 RegDst nPC_sel ALUctr MemWr MemtoReg Equal Rt Rd 0 1 Rs Rt 4 RegWr 5 5 5 busA Rw Ra Rb = busW 00 32 32 32-bit Registers ALU 0 32 busB 32 0 PC 32 Mux Mux Clk 32 WrEn Adr 1 1 Data In Clk Extender Data Memory imm16 PC Ext 32 16 Clk imm16 ExtOp ALUSrc

  26. ALU An Abstract View of the Critical Path • Register file and ideal memory: • The CLK input is a factor ONLY during write operation • During read operation, behave as combinational logic: • Address valid => Output valid after “access time.” Critical Path (Load Operation) = PC’s Clk-to-Q + Instruction Memory’s Access Time + Register File’s Access Time + ALU to Perform a 32-bit Add + Data Memory Access Time + Setup Time for Register File Write + Clock Skew Ideal Instruction Memory Instruction Rd Rs Rt Imm 5 5 5 16 Instruction Address A Data Address 32 Rw Ra Rb 32 Ideal Data Memory 32 32 32-bit Registers PC Next Address Data In B Clk Clk Clk 32

  27. ALU An Abstract View of the Implementation Control Ideal Instruction Memory Control Signals Conditions Instruction Rd Rs Rt 5 5 5 Instruction Address A Data Address Data Out 32 Rw Ra Rb 32 Ideal Data Memory 32 32 32-bit Registers PC Next Address Data In B Clk Clk 32 Clk Datapath

  28. Recap: A Single Cycle Datapath • Rs, Rt, Rd and Imed16 hardwired into datapath from Fetch Unit • We have everything except control signals (underline) • Today’s lecture will show you how to generate the control signals Instruction<31:0> nPC_sel Instruction Fetch Unit Rd Rt <21:25> <16:20> <11:15> <0:15> Clk RegDst 1 0 Mux Rt Rs Rd Imm16 Rs Rt RegWr ALUctr Zero 5 5 5 MemWr MemtoReg busA Rw Ra Rb busW 32 32 32-bit Registers 0 ALU 32 busB 32 0 Clk Mux 32 Mux 32 1 WrEn Adr 1 Data In 32 Data Memory Extender imm16 32 16 Clk ALUSrc ExtOp

  29. Adder Mux Adder Recap: Meaning of the Control Signals • nPC_MUX_sel: 0  PC <– PC + 4 1  PC <– PC + 4 + SignExt(Im16) || 00 • Later in lecture: higher-level connection between mux and branch cond nPC_MUX_sel Inst Memory Adr 4 00 PC imm16 PC Ext Clk

  30. Recap: Meaning of the Control Signals • MemWr: 1  write memory • MemtoReg: 0  ALU; 1  Mem • RegDst: 0  “rt”; 1  “rd” • RegWr: 1  write register • ExtOp: “zero”, “sign” • ALUsrc: 0  regB; 1  immed • ALUctr: “add”, “sub”, “or” RegDst ALUctr MemWr MemtoReg Equal Rt Rd 0 1 Rs Rt RegWr 5 5 5 busA = Rw Ra Rb busW 32 32 32-bit Registers ALU 32 0 busB 32 0 32 Mux Mux Clk 32 WrEn Adr 1 Data In 1 Extender Data Memory imm16 32 16 Clk ExtOp ALUSrc

  31. 31 26 21 16 11 6 0 op rs rt rd shamt funct 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits RTL: The Add Instruction • add rd, rs, rt • mem[PC] Fetch the instruction from memory • R[rd] <- R[rs] + R[rt] The actual operation • PC <- PC + 4 Calculate the next instruction’s address

  32. Inst Memory Adr Adder Mux Adder Instruction Fetch Unit at the Beginning of Add • Fetch the instruction from Instruction memory: Instruction <- mem[PC] • This is the same for all instructions Instruction<31:0> nPC_MUX_sel 4 00 PC Clk imm16 PC Ext

  33. 31 26 21 16 11 6 0 op rs rt rd shamt funct The Single Cycle Datapath during Add • R[rd] <- R[rs] + R[rt] Instruction<31:0> nPC_sel= +4 Instruction Fetch Unit Rd Rt <21:25> <16:20> <11:15> <0:15> Clk RegDst = 1 1 0 Mux ALUctr = Add Rt Rs Rd Imm16 Rs Rt RegWr = 1 5 5 5 MemtoReg = 0 busA Zero MemWr = 0 Rw Ra Rb busW 32 32 32-bit Registers 0 ALU 32 busB 32 0 Clk Mux 32 Mux 32 1 WrEn Adr 1 Data In 32 Data Memory Extender imm16 32 16 Clk ALUSrc = 0 ExtOp = x

  34. Inst Memory Adr Adder Mux Adder Instruction Fetch Unit at the End of Add • PC <- PC + 4 • This is the same for all instructions except: Branch and Jump Instruction<31:0> nPC_MUX_sel 4 0 00 PC 1 Clk imm16

  35. 31 26 21 16 0 op rs rt immediate The Single Cycle Datapath during Or Immediate • R[rt] <- R[rs] or ZeroExt[Imm16] Instruction<31:0> nPC_sel = Instruction Fetch Unit Rd Rt <21:25> <16:20> <11:15> <0:15> Clk RegDst = 1 0 Mux Rt Rs Rd Imm16 Rs Rt ALUctr = RegWr = 5 5 5 MemtoReg = busA Zero MemWr = Rw Ra Rb busW 32 32 32-bit Registers 0 ALU 32 busB 32 0 Clk Mux 32 Mux 32 1 WrEn Adr 1 Data In 32 Data Memory Extender imm16 32 16 Clk ALUSrc = ExtOp =

  36. 31 26 21 16 0 op rs rt immediate The Single Cycle Datapath during Load • R[rt] <- Data Memory {R[rs] + SignExt[imm16]} Instruction<31:0> nPC_sel= +4 Instruction Fetch Unit Rd Rt <21:25> <16:20> <11:15> <0:15> Clk RegDst = 0 1 0 Mux ALUctr = Add Rt Rs Rd Imm16 Rs Rt RegWr = 1 MemtoReg = 1 5 5 5 busA Zero MemWr = 0 Rw Ra Rb busW 32 32 32-bit Registers 0 ALU 32 busB 32 0 Clk Mux 32 Mux 1 WrEn Adr 1 Data In 32 Data Memory Extender 32 imm16 32 16 Clk ALUSrc = 1 ExtOp = 1

  37. 31 26 21 16 0 op rs rt immediate The Single Cycle Datapath during Store • Data Memory {R[rs] + SignExt[imm16]} <- R[rt] Instruction<31:0> nPC_sel = Instruction Fetch Unit Rd Rt <21:25> <16:20> <11:15> <0:15> Clk RegDst = 1 0 Mux Rt Rs Rd Imm16 Rs Rt ALUctr = RegWr = 5 5 5 MemtoReg = busA Zero MemWr = Rw Ra Rb busW 32 32 32-bit Registers 0 ALU 32 busB 32 0 Clk Mux 32 Mux 32 1 WrEn Adr 1 Data In 32 Data Memory Extender imm16 32 16 Clk ALUSrc = ExtOp =

  38. 31 26 21 16 0 op rs rt immediate The Single Cycle Datapath during Store • Data Memory {R[rs] + SignExt[imm16]} <- R[rt] Instruction<31:0> nPC_sel= +4 Instruction Fetch Unit Rd Rt <21:25> <16:20> <11:15> <0:15> Clk RegDst = x 1 0 Mux ALUctr = Add Rt Rs Rd Imm16 Rs Rt RegWr = 0 5 5 5 MemtoReg = x busA Zero MemWr = 1 Rw Ra Rb busW 32 32 32-bit Registers 0 ALU 32 busB 32 0 Clk Mux 32 Mux 32 1 WrEn Adr 1 32 Data In Data Memory Extender imm16 32 16 Clk ALUSrc = 1 ExtOp = 1

  39. 31 26 21 16 0 op rs rt immediate The Single Cycle Datapath during Branch • if (R[rs] - R[rt] == 0) then Zero <- 1 ; else Zero <- 0 Instruction<31:0> nPC_sel= “Br” Instruction Fetch Unit Rd Rt <21:25> <16:20> <11:15> <0:15> Clk RegDst = x 1 0 Mux Rt Rs Rd Imm16 Rs Rt ALUctr =Sub RegWr = 0 MemtoReg = x 5 5 5 busA Zero MemWr = 0 Rw Ra Rb busW 32 32 32-bit Registers 0 ALU 32 busB 32 0 Clk Mux 32 Mux 32 1 WrEn Adr 1 Data In 32 Data Memory Extender imm16 32 16 Clk ALUSrc = 0 ExtOp = x

  40. 31 26 21 16 0 op rs rt immediate Inst Memory Adr Adder Mux Adder Instruction Fetch Unit at the End of Branch • if (Zero == 1) then PC = PC + 4 + SignExt[imm16]*4 ; else PC = PC + 4 Instruction<31:0> nPC_sel Zero • What is encoding of nPC_sel? • Direct MUX select? • Branch / not branch • Let’s choose second option nPC_MUX_sel 4 0 00 PC 1 Clk imm16

  41. Step 4: Given Datapath: RTL -> Control Instruction<31:0> Inst Memory <21:25> <21:25> <16:20> <11:15> <0:15> Adr Op Fun Rt Rs Rd Imm16 Control ALUctr MemWr MemtoReg ALUSrc RegWr RegDst ExtOp Zero nPC_sel DATA PATH

  42. A Summary of Control Signals inst Register Transfer ADD R[rd] <– R[rs] + R[rt]; PC <– PC + 4 ALUsrc = RegB, ALUctr = “add”, RegDst = rd, RegWr, nPC_sel = “+4” SUB R[rd] <– R[rs] – R[rt]; PC <– PC + 4 ALUsrc = RegB, ALUctr = “sub”, RegDst = rd, RegWr, nPC_sel = “+4” ORi R[rt] <– R[rs] + zero_ext(Imm16); PC <– PC + 4 ALUsrc = Im, Extop = “Z”, ALUctr = “or”, RegDst = rt, RegWr, nPC_sel = “+4” LOAD R[rt] <– MEM[ R[rs] + sign_ext(Imm16)]; PC <– PC + 4 ALUsrc = Im, Extop = “Sn”, ALUctr = “add”, MemtoReg, RegDst = rt, RegWr, nPC_sel = “+4” STORE MEM[ R[rs] + sign_ext(Imm16)] <– R[rs]; PC <– PC + 4 ALUsrc = Im, Extop = “Sn”, ALUctr = “add”, MemWr, nPC_sel = “+4” BEQ if ( R[rs] == R[rt] ) then PC <– PC + sign_ext(Imm16)] || 00 else PC <– PC + 4 nPC_sel = “Br”, ALUctr = “sub”

  43. add sub ori lw sw beq jump RegDst 1 1 0 0 x x x ALUSrc 0 0 1 1 1 0 x MemtoReg 0 0 0 1 x x x RegWrite 1 1 1 1 0 0 0 MemWrite 0 0 0 0 1 0 0 nPCsel 0 0 0 0 0 1 0 Jump 0 0 0 0 0 0 1 ExtOp x x 0 1 1 x x ALUctr<2:0> Add Subtract Or Add Add xxx Subtract 31 26 21 16 11 6 0 R-type op rs rt rd shamt funct add, sub immediate I-type op rs rt ori, lw, sw, beq J-type op target address jump A Summary of the Control Signals See func 100000 100010 We Don’t Care :-) Appendix A op 000000 000000 001101 100011 101011 000100 000010

  44. op 00 0000 00 1101 10 0011 10 1011 00 0100 00 0010 R-type ori lw sw beq jump RegDst 1 0 0 x x x ALUSrc 0 1 1 1 0 x MemtoReg 0 0 1 x x x RegWrite 1 1 1 0 0 0 MemWrite 0 0 0 1 0 0 Branch 0 0 0 0 1 0 Jump 0 0 0 0 0 1 ExtOp x 0 1 1 x x ALUop<N:0> “R-type” Or Add Add xxx Subtract ALU Control (Local) The Concept of Local Decoding func ALUctr op 6 Main Control 3 ALUop 6 N ALU

  45. func ALU Control (Local) op 6 ALUctr Main Control ALUop 6 3 N R-type ori lw sw beq jump ALUop (Symbolic) “R-type” Or Add Add xxx Subtract ALUop<2:0> 1 00 0 10 0 00 0 00 xxx 0 01 The Encoding of ALUop • In this exercise, ALUop has to be 2 bits wide to represent: • (1) “R-type” instructions • “I-type” instructions that require the ALU to perform: • (2) Or, (3) Add, and (4) Subtract • To implement the full MIPS ISA, ALUop has to be 3 bits to represent: • (1) “R-type” instructions • “I-type” instructions that require the ALU to perform: • (2) Or, (3) Add, (4) Subtract, and (5) And (Example: andi)

  46. func ALU Control (Local) op 6 ALUctr Main Control ALUop 6 3 N R-type ori lw sw beq jump ALUop (Symbolic) “R-type” Or Add Add xxx Subtract ALUop<2:0> 1 00 0 10 0 00 0 00 xxx 0 01 31 26 21 16 11 6 0 R-type op rs rt rd shamt funct P. 286 text: funct<5:0> Instruction Operation ALUctr ALUctr<2:0> ALU Operation 10 0000 add 000 And 10 0010 subtract 001 Or 10 0100 and 010 Add ALU 10 0101 or 110 Subtract 10 1010 set-on-less-than 111 Set-on-less-than The Decoding of the “func” Field

  47. R-type ori lw sw beq ALUop (Symbolic) “R-type” Or Add Add Subtract ALUop<2:0> 1 00 0 10 0 00 0 00 0 01 ALUop func ALU Operation ALUctr bit<2> bit<1> bit<0> bit<3> bit<2> bit<1> bit<0> bit<2> bit<1> bit<0> 0 0 0 x x x x Add 0 1 0 0 x 1 x x x x Subtract 1 1 0 0 1 x x x x x Or 0 0 1 1 x x 0 0 0 0 Add 0 1 0 1 x x 0 0 1 0 Subtract 1 1 0 1 x x 0 1 0 0 And 0 0 0 1 x x 0 1 0 1 Or 0 0 1 1 x x 1 0 1 0 Set on < 1 1 1 The Truth Table for ALUctr funct<3:0> Instruction Op. 0000 add 0010 subtract 0100 and 0101 or 1010 set-on-less-than

  48. The Logic Equation for ALUctr<2> ALUop func bit<2> bit<1> bit<0> bit<3> bit<2> bit<1> bit<0> ALUctr<2> • ALUctr<2> = !ALUop<2> & ALUop<0> + ALUop<2> & !func<2> & func<1> & !func<0> 0 x 1 x x x x 1 1 x x 0 0 1 0 1 1 x x 1 0 1 0 1 This makes func<3> a don’t care

  49. The Logic Equation for ALUctr<1> ALUop func bit<2> bit<1> bit<0> bit<3> bit<2> bit<1> bit<0> ALUctr<1> • ALUctr<1> = !ALUop<2> & !ALUop<1> + ALUop<2> & !func<2> & !func<0> 0 0 0 x x x x 1 0 x 1 x x x x 1 1 x x 0 0 0 0 1 1 x x 0 0 1 0 1 1 x x 1 0 1 0 1

  50. The Logic Equation for ALUctr<0> ALUop func bit<2> bit<1> bit<0> bit<3> bit<2> bit<1> bit<0> ALUctr<0> • ALUctr<0> = !ALUop<2> & ALUop<1> + ALUop<2> & !func<3> & func<2> & !func<1> & func<0> + ALUop<2> & func<3> & !func<2> & func<1> & !func<0> 0 1 x x x x x 1 1 x x 0 1 0 1 1 1 x x 1 0 1 0 1

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