Ch 3. Digital Circuits

1. Ch3. Digital Circuits 3.1 Logic Signals and Gates • N bits can represent states • (When N=1, 2 states)

2. Input • Output • Black-box • Black-box representation and Truth table shows a logic circuit with input/output and ignores electrical behavior ofthe circuit

3. AND gate produces ‘1’ : Only if all of its inputs are ‘1’ • OR gate produces ‘1’ : One or more of its inputs are ‘1’ • NOT gate produces an output that is opposite of its input value

4. NAND Gate : Opposite of an AND gate’s output • NOR Gate : Opposite of an OR gate’s output

5. Black-box representation Truth table

6. Input • Lag • Lag • Lag Output • Timing diagram show how the circuit might respond • to a time-varying pattern of input signals

7. 3.3 CMOS Logic • Not expected tooccur except during signal transition

8. NMOS • Turn on when • PMOS • Turn on when • High resistance : “Off” Transistor • Low resistance : “On” Transistor

9. PMOS, Turn on when • NMOS, Turn on when

10. PMOS PMOS NMOS NMOS

11. CMOS inverter

12. 둘 중 하나만 On되어도 Z=‘1’ • 둘 다 On 되어야 Z=‘0’

13. PMOS PMOS PMOS NMOS NMOS NMOS

14. 둘 다 On 되어야 Z=‘1’ • 둘 중 하나만 On되어도 Z=‘0’

16. D PMOS는 F를 이용 PMOS는 F를 이용 A B = F = D C F F NMOS는 F’를 이용 NMOS는 F’를 이용 C A = = F’ = D B • AND -> Series • OR -> Parallel

17. PMOS는 F를 이용 NMOS는 F’를 이용 • AND -> Series • OR -> Parallel

19. Inverter + Inverter

20. NAND + Inverter • More Transistors are needed than NAND

22. 6 Transistor • 4 Transistor • 6 Transistor • 4x3+2 =14 Transistor • 16 Transistor

24. 6 Transistor • 4 Transistor • 6 Transistor • 4x3+2 =14 Transistor • 16 Transistor

25. 3.4 Electrical Behavior of CMOS Circuits

27. 3.5 CMOS Static Electrical Behavior • Noise can be added in signals • So, There are noise margins

28. High state에서는 Minimum value 고려 • : Min input voltage guaranteed to be recognized as high • Low state에서는 Maximum value 고려 • : Max input voltage guaranteed to be recognized as low • : Max output voltage produced in low state • : Min output voltage produced in high state

29. Not CMOS resistive load

30. When

31. When

32. (TTL load) • (TTL load)

34. Sink current • Source current

38. Pull-up • Pull-down

39. No Transition Time in ideal case • (80% ~ 20%) • (20% ~ 80%)

40. 3.6 CMOS Dynamic Electrical Behavior • Both the speed and the power consumption of a CMOS device depend to a large extent on “AC” device

41. High State • Low State

43. Low State • High State

45. Ideal case (No rise and fall times) • 50% • 50% • Propagation delay

46. (internal power dissipation due to output transition) (Power due to load capacitor)

49. 3.7 Other CMOS input and Output Structures