1. Implementing Digital Circuits Lecture L3.1

2. Implementing Digital Circuits • Transistors and Integrated Circuits • Transistor-Transistor Logic (TTL) • Programmable Logic Devices • PLDs and CPLDs • Field Programmable Gate Arrays (FPGAs) • The Xilinx Spartan 3 • The Xilinx Virtex Family

3. Discovery of the Electron -- 1898 Cathode Tube J. J. Thomson Electric Field -- “corpuscle” Cavendish Labs

4. The Vacuum Tube

5. Bell Labs Museum The FirstPoint-Contact Transistor1947

6. Bell Labs The FirstJunction Transistor1951 M1752 Outside the Lab Lab model

7. Texas Instrument’s First IC -- 1958 Jack Kilby Robert Noyce Fairchild Intel

8. Moore’s Law

9. Moore’s Law

10. Implementing Digital Circuits • Transistors and Integrated Circuits • Transistor-Transistor Logic (TTL) • Programmable Logic Devices • PLDs and CPLDs • Field Programmable Gate Arrays (FPGAs) • The Xilinx Spartan 3 • The Xilinx Virtex Family

11. Transistor-Transistor Logic (TTL) • Developed in mid-1960s • Large family (74xx) of chips from basic gates to arithmetic logic units • Becoming obsolete with the development of programmable logic devices (PLDs)

12. Transistor-Transistor Logic (TTL) Diode-Transistor Logic DTL Transistor-Transistor Logic (TTL) "Totem Pole" output

13. TTL Chips

14. TTL NAND, NOR, XOR

15. TTL Multiple-input Gates

16. Small-Scale Integrated (SSI) Circuits • 1 to 10 gates • NAND gate has 4 transistors

17. Medium-Scale Integrated (MSI) Circuits • 10-100 gates • Adders • Comparators • Multiplexers • Decoders

18. Large-Scale Integrated (LSI) Circuits • 100-1000 gates • Arithmetic Logic Units

19. Very-Large-Scale Integrated (VLSI) Circuits • >1000 gates • Microprocessors • Programmable Logic Devices (PLDs) • Complex Programmable Logic Devices (CPLDs) • Field Programmable Gate Arrays (FPGAs)

20. Implementing Digital Circuits • Transistors and Integrated Circuits • Transistor-Transistor Logic (TTL) • Programmable Logic Devices • PLDs and CPLDs • Field Programmable Gate Arrays (FPGAs) • The Xilinx Spartan 3 • The Xilinx Virtex Family

21. A Programmable Logic Device

22. A Programmable Logic Device A = X & !X & Y & !Y = 0 & 0 = 0

23. A Programmable Logic Device A = X & !X & Y & !Y = 0 & 0 = 0 Z = A # B = 0 # B = B

24. Alternate PLD Representation

25. Make PLD Connections for AND X Y A X X 1 Z X X X X 2 B X !X Y !Y

26. Make PLD Connections for OR X Y A X 1 Z X 2 B X !X Y !Y

27. Make PLD Connections for NAND X Y A X 1 Z X 2 B X !X Y !Y

28. Make PLD Connections for NOR X Y A X X 1 Z X X X X 2 B X !X Y !Y

29. Make PLD Connections for XNOR X Y A X X 1 Z X X 2 B A B C 0 0 1 0 1 0 1 0 0 1 1 1 X !X Y !Y

30. Make PLD Connections for XOR X Y A X X 1 Z X X 2 B A B C 0 0 0 0 1 1 1 0 1 1 1 0 X !X Y !Y

31. 1 20 Vcc I/CLK 2 19 I I/O 3 18 I/O I 4 17 I I/O 5 16 I I/O 6 15 I I/O 7 14 I I/O 8 13 I I/O 9 12 I I/O 10 11 GND I/OE GAL 16V8 The GAL 16V8

32. Structure of the GAL 16V8 PLD

33. GAL 16V8 Polarity Control OE A C Pin B Polarity X X closed B = 0 C = A ­ open B = 1 C = !A

34. OE CLK D Q Pin CLK !Q Polarity X Feedback CLK Typical PLD Flip-Flops

35. Structure of the GAL 16V8 PLD

36. 3 In-System Programming Controller JTAG Controller JTAG Port Function Block1 I/O I/O Function Block 2 I/O I/O Blocks FastCONNECT Switch Matrix I/O Function Block 3 Global Clocks 3 Global Set/Reset 1 Function Block 4 Global Tri-States 2 or 4 XC9500 CPLDs • 5 volt in-system programmable (ISP) CPLDs • 5 ns pin-to-pin • 36 to 288 macrocells (6400 gates) • Industry’s best pin-locking architecture • 10,000 program/erase cycles • Complete IEEE 1149.1 JTAG capability

37. Global Clocks Global Tri-State 2 or 4 3 I/O Macrocell 1 Product- Term Allocator AND Array 36 From FastCONNECT I/O Macrocell 18 To FastCONNECT XC9500 Function Block Each function block is like a 36V18 !

38. XC9500 Product Family 9536 9572 95108 95144 95216 95288 Macrocells 36 72 108 144 216 288 Usable Gates 800 1600 2400 3200 4800 6400 tPD (ns) 5 7.5 7.5 7.5 10 10 Registers 36 72 108 144 216 288 Max I/O 34 72 108 133 166 192 VQ44 PC44 PC44 PC84 TQ100 PQ100 PC84 TQ100 PQ100 PQ160 PQ100 PQ160 Packages HQ208 BG352 PQ160 HQ208 BG352

39. PLDT-3 Buttons Xilinx XC95108 CPLD 7 segment display Switches LEDs

40. Xilinx 95108 • 6 function blocks • Each contains 18 macro cells • Each macro cell behaves like a GAL32V18 • AND-OR array for sum-of-products • 32 inputs and 18 outputs

41. Architecture of the Xilinx XC95108 CPLD

42. Controlled inverter Each Xilinx 95108 macrocell contains a D flip-flop

43. Each Xilinx 95108 macrocell contains a D flip-flop Note asynchronous preset x z y Note asynchronous reset

44. Implementing Digital Circuits • Transistors and Integrated Circuits • Transistor-Transistor Logic (TTL) • Programmable Logic Devices • PLDs and CPLDs • Field Programmable Gate Arrays (FPGAs) • The Xilinx Spartan 3 • The Xilinx Virtex Family

46. Block diagram of Xilinx Spartan-3 FPGA

47. Each Spartan-3 CLB contains four CLB slices

48. Left-hand Slice SLICEM

49. Top of Left-hand Slice SLICEM

50. 16 x 1 SRAM Lookup Table