Unit 3 Protected Mode Architecture
Points to be covered… • TLB • Page level protection • Introduction • Segmentation • Support registers • Related instructions • Descriptors • Memory management through segmentation • Logical to linear address translations • Protection by segmentation • Privilege-level • Protection • Related instructions • Inter-privilege level • Transfer control • Paging-support registers • Related data structures • Linear to physical address translation
Related instructions • ARPL • CLTS • CPUID • LAR • LGDT • LIDT • LMSW • LLDT • LSL • LTR • MOV • RDTSC • SGDT • SIDT • SLDT • SMSW • STR • VERR • VERW
A selector that has an index value of zero & points to the GDT is called as null selector. • This selector is used to provide a method of initializing segment registers, since any access right using selector generates an exception.
Protecting Segmented Accesses • Type Check • Limit Check • Addressable domain check • Procedure entry point check • Privileged instruction check
1. Type Check • Type checking is used to determine whether the current memory access (read/write) is allowed • Example: • Read-Only Data Segment (memory write) • Execute-Only segment (Read) • The types of accesses allowed are based on individual bits in the data & code segment descriptors • Writable bits ( DS descriptor) • Readable bits (CS descriptor)
2. Limit Check • Limit bits= 20 bits • G bit • G = 0 ; 64KB Physical memory size • G = 1 ; 4 KB Pages stored in memory (memory size = 4Kb to 4Gb)
3. Addressable domain check • The addressable domain of a task is a function of the task’s CPL. • CPL=0 Highest privilege 0 -> 0,1,2,3 1 -> 1,2,3 2 -> 2,3 3 -> 3
4. Procedure entry point check • Call gate
5. Privileged instruction check Some instructions are privileged & may only be executed when the CPL = 0 • CLTS • HLT • INVD • INVLPG • WBINVD • MOV to/from CR • MOV to/from DR • LGDT • LLDT • LIDT • LMSW • LTR Clear Task switching flag in CR0 Invalidate Internal Cache Invalidates (flushes) the translation look aside buffer (TLB) entry specified with the source operand. Write Back and Invalidate Cache
Description • Moves the contents of a control register (CR0, CR2, CR3, or CR4) to a general-purpose register or vice versa. The operand size for these instructions is always 32 bits, regardless of the operand-size attribute. • When loading a control register, a program should not attempt to change any of the reserved bits; that is, always set reserved bits to the value previously read. Operation • DEST SRC; Flags Affected • The OF, SF, ZF, AF, PF, and CF flags are undefined.
Introduction • The architecture of Pentium protected mode is different than real mode • PE bit = 0 [Enter into protected mode] • Features / advantages provided by Pentium: • Segmentation & Paging • Protection • Multitasking • It allows the processor to run all 8086 & 80286 programs • Virtual addressing increases memory • It increases linear address space to 4 GB & allows the running virtual memory pgms of approximately unlimited size (64 terabytes)
Segmentation • Advantages of segmentation: • Provides powerful memory mgmt mechanism • The segmented structure of Pentium mem. Space supports modular s/w design • Segments provide a way to easily implement object oriented pgms • It allows two processes to easily share data • Segmentation makes it possible to separate the mem. areas for stack, data & code