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Introduction to Sequential Logic Design

This introduction to sequential logic design covers the foundational concepts of flip-flops and latches, which serve as the building blocks of sequential circuits. A latch is a bistable memory device with level-sensitive triggering that continuously monitors inputs, while a flip-flop is edge-triggered, changing outputs only at specific clock times. We delve into the functionality of various types of D flip-flops, including positive and negative-edge triggered variants, as well as their timing parameters and usage in testing through scan flip-flops. Explore the importance of flip-flops in building reliable sequential circuits.

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Introduction to Sequential Logic Design

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  1. Introduction to Sequential Logic Design Flip-flops

  2. Prev… • Latches • S-R • S-bar-R-bar • S-R with enable signal • D

  3. FF vs. Latch • Latches and flip-flops (FFs) are the basic building blocks of sequential circuits. • latch: bistable memory device with level sensitive triggering (no clock), watches all of its inputs continuously and changes its outputs, independent of a clocking signal. • flip-flop: bistable memory device with edge-triggering (with clock), samples its inputs, and changes its output only at times determined by a clocking signal.

  4. Edge triggered D Flip-Flop • A D FF combines a pair of D latches. Master/slave • D FF • Positive-edge-triggered D FF • Negative-edge-triggered D FF • Edge-Triggered D FF with Enable • Scan FF

  5. Positive-Edge-triggered D flip-flop

  6. Dynamic-input indicator Positive-Edge-triggered D flip-flop

  7. Edge-triggered D flip-flop behavior

  8. Edge-triggered D flip-flop behavior

  9. Edge-triggered D flip-flop behavior

  10. D flip-flop timing parameters • Propagation delay (from CLK) • Setup time (D before CLK) • Hold time (D after CLK)

  11. D FF with asynchronous inputs Force the D FF to a particular state independent of the CLK and D inputs. PR (Preset) and CLR (Clear)

  12. Negative-edge triggered D FF • Simply inverts the clock input. Active low.

  13. Negative-edge triggered D FF • Simply inverts the clock input. Active low.

  14. Edge-triggered D FF with Enable

  15. Scan FF Scan flip-flops -- for testing • TE = 0 ==> normal operation • TE = 1 ==> test operation • All of the flip-flops are hooked together in a daisy chain from external test input TI. • Load up (“scan in”) a test pattern, do one normal operation, shift out (“scan out”) result on TO.

  16. J-K flip-flops • Not used much anymore

  17. T (toggle) flip-flops • A T FF changes state on every tick of the clock. (be toggled on every tick) • Q has precisely half the frequency of the T. • Important for counters • Positive-edge-triggered T FF

  18. T (toggle) flip-flops with enable

  19. T (toggle) flip-flops with enable

  20. Next… • FSM analysis • Read Ch-7.3

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