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Built-In Self-Test for Radio Frequency System-On-Chip PowerPoint Presentation
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Built-In Self-Test for Radio Frequency System-On-Chip

Built-In Self-Test for Radio Frequency System-On-Chip

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Built-In Self-Test for Radio Frequency System-On-Chip

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  1. Built-In Self-Test for Radio Frequency System-On-Chip Bruce Kim The University of Alabama

  2. Outline • Proposed BIST Architecture • Developed Equations • Measurement Results • Conclusions

  3. Motivation Today Future System-On-Board (SOB) System-On-Chip (SOC)

  4. RF Testing • Expensive • Labor intensive

  5. What is BIST (Built-In Self-Test)? A test technique which allows the SOC to evaluate its own quality without expensive external equipment.

  6. Test Flow Package Functional Test Singulated Wafer Level Testing Proposed BIST Functional Testing Proposed BIST (Go-No Go)

  7. LO LO VGA ADC ADC DAC DAC Wireless Radio LNA Phase Shifter DSP Duplexer LO VGA Phase Shifter PA

  8. Proposed RF BIST for LNA • S1 closed: Measure VT1 • S2 & S3 closed:Measure VT2

  9. Proposed RF BIST Hardware

  10. Equivalent Circuit Model

  11. (1) (2) (3) Development of Equations

  12. : Voltage gain of BIST : Voltage gain of Test Amplifier Fault-Free Input Impedance

  13. Faulty-Case Input Impedance(VT2) : Voltage gain of BIST under faulty case

  14. : Voltage gain of BIST Fault-Free Voltage Gain

  15. : Voltage gain of BIST under faulty case Faulty-Case Voltage Gain (VT1, VT2)

  16. Input Return Loss • Fault-Free Case : Input Return Loss of BIST • Faulty Case

  17. Output Signal-to-Noise Ratio • Fault-Free Case kT: -204 dB B: signal bandwidth • Faulty Case

  18. Summary of Equations

  19. 5GHz Low Noise Amplifier 0.18m SiGe HBT Technology

  20. Small-Signal Model for 5GHz LNA Stage 2 • Hybrid-π model for HBT with series resistance and two capacitances • Inductor model with series resistance • Stage 2: same topology as stage 1

  21. Validation Procedure& System Calibration • Test VT2for Gain=3 RF BIST Circuit

  22. Programmable Capacitor Banks for CB (D3D2D1)= (001) for 5.25GHz, (011) for 2.4GHz and (111) for 1.8GHz

  23. PD2 TA Chip Micrograph PD1 BIST block

  24. Defect Models • Defect Models for Actives

  25. Defect Models • Defect Models for Passives

  26. Measurement Set-Up for LNA and TA S3 V L LNA S1 W Z =50 L S2 v in W V R =50 s T 1 P D 1 Labview V Board V T2 T T A PD2

  27. Fault-Free Wafer Level Testing for Catastrophic Faults

  28. Wafer Level Testing for Parametric Variations Fault Free Device Tolerance: 20% Good Device

  29. Results • Measured Values mean that external equipment was used. • Simulation results are from ADS commercial software. • Modeling results are from the Hybrid-p and other passives modeling in the LNA circuit.

  30. Input Impedance of TA

  31. Gain of TA

  32. Input Impedances

  33. Gains

  34. Input Return Losses

  35. Input VSWRs

  36. Data Summary

  37. SoC Transceiver System Auto Compensation RF Filter RF Filter IF Filter Amp. Amp. Antenna ADC Amp. Digital Signal Processor RF Filter VCO Phase filter PLL VCO Switch PLL IF Filter Amp. DAC Amp. RF Filter Power amp. Attenuator RF Filter IF Filter

  38. Parametric Variations

  39. Capacitor Mirror Banks (CMB) N = 8-bit: When (D11D10…D5D4)= (00…01), CB = Cb/8

  40. Lc1 Parametric Variations Lc1: Most sensitive component in LNA

  41. Changes of Cb1 to Compensate Gain

  42. Gain Compensations Lc1: Most gain-sensitive component in LNA

  43. Noise Figure Compensations

  44. Programmable RF BIST Technique PC S3 v L LNA W Z =50 S1 L CMB v S2 in v W L 1 R =50 s V BIST A/D T 1 v T Labview V T2 LNA Under Test D N External Board • Used for GSM, Bluetooth, IEEE802.11g

  45. Test Technique Comparison

  46. Limitation

  47. On-going Work • Construct automatic test structure with on-chip BIST structure and relays on a load board • Develop a LabView software for test automation

  48. Conclusions • Introduced a new low-cost RF test hardware. • Successful with programmable RF test for different standards. • Self-compensation network for process and thermal variations.