1 / 16

Built-In Self-Test of Global Routing Resources in Virtex-4 FPGAs

BIST. Auburn University. Built-In Self-Test. Built-In Self-Test of Global Routing Resources in Virtex-4 FPGAs. Jia Yao, Bobby Dixon, Charles Stroud and Victor Nelson Dept. of Electrical & Computer Engineering Auburn University. Outline of Presentation. Motivation and background

cricket
Télécharger la présentation

Built-In Self-Test of Global Routing Resources in Virtex-4 FPGAs

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. BIST Auburn University Built-In Self-Test Built-In Self-Test of Global Routing Resources in Virtex-4 FPGAs Jia Yao, Bobby Dixon, Charles Stroud and Victor Nelson Dept. of Electrical & Computer Engineering Auburn University

  2. Outline of Presentation • Motivation and background • Virtex-4 global routing resource • Routing BIST Implementation for Virtex-4 FPGAs • Implementation results • Application to Virtex-5 • Summary North Atlantic Test Workshop 2

  3. Fault Simulation Results • Stuck-at Fault • Stuck-at value • Feedback wires can be considered under test • Bridging Fault • Best approaches • 8-bit maximum length sequence CAR • cross-coupled parity J. Yao 5/15/08 North Atlantic Test Workshop

  4. Slice 3 Slice 1 Slice 2 Slice 0 ORA (Oo) odd parity Podd Cu1 Cu0 Pass /Fail G LUT ORA even parity ORA (Oe) even parity Peven Cd1 Cd0 Pass /Fail G LUT ORA odd parity Podd 2 1 1 2 Cd1 TPG (To) count-down odd parity Peven G LUT Cu1 Cd0 G LUT TPG (Te) count-up even parity Cu0 F LUT F LUT Cross-Coupled Parity Approach North Atlantic Test Workshop J. Yao 5/15/08

  5. Virtex-4 Global Routing Resources • CLB • Switch Box • Slices (LUTs & FFs) • PIPs • Double/Hex lines • N/S/E/W • 10 wires • BEG, MID, END • Long Lines N/S 2 BEG 0-9 Switch Box slices N/S 2 MID 0-9 N/S 2 END 0-9 Long lines North Atlantic Test Workshop J. Yao 5/15/08

  6. Te BEG 0-9 Oo Oe MID 0-9 To END 0-9 Oo Oe To BEG 0-9 Oo Oe MID 0-9 Te Oe END 0-9 Oo Te BEG 0-9 Oo Oe MID 0-9 To Oo END 0-9 Oe BIST for Double lines (North and South) • Pass by 1 CLB into MID pass by 2 CLBs into END • 6 wires under test (2 configs) • 12 lines under test in parallel • Alternate TPGs, ORAs position in adjacent CLBs. North Atlantic Test Workshop J. Yao 5/15/08

  7. Loopback Connections South END-to-BEG Connections Loopbacks • At the edges of array • via wires in the opposite direction till the opposite edge • Example: north double lines loopback at the top edge North Atlantic Test Workshop J. Yao 5/15/08

  8. BIST for Double lines (East and West) • Involve Non-CLB Columns • END and BEG terminals in east and west directions are connected J. Yao 5/15/08 North Atlantic Test Workshop

  9. Non-CLB Column Double Lines • BIST for Non-CLB Column Double Lines • TPGs and ORAs locate in adjacent CLB columns • Use east/west double lines to connect adjacent CLB columns J. Yao 5/15/08 North Atlantic Test Workshop

  10. BIST For Hex Lines • Hex lines architecture • pass by 3 CLBs into MID, by 6 CLBs into END • more limitation of connections from hex lines to LUTs • MID and END terminals share the same PIPs • BIST for hex lines • similar to double lines • more configurations needed North Atlantic Test Workshop J. Yao 5/15/08

  11. Long Lines Architecture i+25 • pass by 24 CLBs • 5 wire segments 4 wires under test • Bi-directional • two end points: source or input • other three stops: input only • Orthogonal direction is tested simultaneously i+24 i+19 i+18 i+13 i+12 i+7 i+6 i+1 i North Atlantic Test Workshop J. Yao 5/15/08

  12. Pass /Fail G LUT Peven Cd0-3 ORA even parity (Oe) F LUT BIST for Long lines Peven Tcd Oe Oe CLB i+5 CLB i+24 Tcu Cu2 Oe CLB i+4 Oe Tcd CLB i+18 Oe Cu1 CLB i+3 Oe Tcu CLB i+12 Oe Cuo CLB i+2 Oe Tcd CLB i+6 Oe Peven CLB i+1 Tcu Oe Oe CLB i CLB i J. Yao 5/15/08 North Atlantic Test Workshop

  13. Global Routing BIST Configurations J. Yao 5/15/08 North Atlantic Test Workshop

  14. RAM RAM I/O Cell DSP MIDDLE Actual Implementation Results J. Yao 5/15/08 North Atlantic Test Workshop

  15. Application to Virtex-5 • Global Routing Resource changed • double lines, pent lines and long lines • N/S/E/W • BEG, MID, END • half as the same, half as “L-shaped” which go in orthogonal direction as well • 3 wires for each pattern in each direction instead of 10 • long lines pass by 18 CLBs, four wires • Our approach is adapted to Virtex-5 • test for “L-shaped” double/pent lines North Atlantic Test Workshop J. Yao 5/15/08

  16. Summary • Cross-coupled Parity is the best choice • better fault coverage • the most practical for actual implementation • best choice for Virtex-5 • BIST of Virtex-4 routing resources • Program to generate BIST configurations automatically • modified for V-5 J. Yao 5/15/08 North Atlantic Test Workshop

More Related