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## Built-In Self-Test and Calibration of Mixed-Signal Devices

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**Built-In Self-Test and Calibration of Mixed-Signal Devices**Advisor: Vishwani D. Agrawal University Reader Minseo Park Committee Members: Fa F. Dai Victor P. Nelson Adit D. Singh Ph.D Final Exam Wei Jiang March 24 2011**Outline**• Introduction • Background • BIST Architecture for Mixed-Signal Devices • Overview of Proposed Architecture • Test of DAC/ADC • Calibration of DAC • Sigma-Delta Modulation • Polynomial Fitting Algorithm • Conclusion Wei Jiang**Motivation**• Digital BIST techniques • Defect-oriented • Logic BIST, scan chain, boundary scan, JTAG, etc • Mixed-Signal BIST techniques • Specification-oriented • No universally accepted standard • Issues • Parameter deviation • Process variation Wei Jiang**Approach**• Problem • Design a post-fabrication variation-tolerant process-independent technique for mixed-signal devices • Solution • Test and characterize mixed-signal devices using digital circuitry • Use DSP as BIST controller for test pattern generation (TPG) and output data analysis (ORA) • Calibrate mixed-signal devices Wei Jiang**Mixed-Signal Devices**• Both digital and analog circuitry in single die • DSP usually embedded for data processing • Analog circuitry controllable by digital part • Converters • Analog-to-digital converter (ADC) • Flash ADC, successive-approximation ADC, Pipeline ADC, Sigma-Delta ADC • Digital-to-analog converter (DAC) • PWM/Oversampling DAC, Binary-weighted DAC Wei Jiang**Testing of Mixed-Signal Devices**• Both digital and analog circuitry need test • Defects and faults • Catastrophic faults (hard faults) • Parametric faults (soft faults) • Test approaches • Functional test (specification oriented) • Structural test (defect oriented) Wei Jiang**Digital BIST**Conventional logic BIST technology LFSR-based random test; Scan-based deterministic test DSP can be TPG and ORA Digital circuitry must be fault-free before being used for mixed-signal test May be hardware or software based Wei Jiang**Faulty Mixed-Signal Circuitry**• Good circuitry • All parameters and characteristics are within pre-defined specified range • Fault-tolerance factor • Post-fabrication and software-controllable • Trade-off between fault-tolerance of parameter deviation and calibration resolution • Larger value for wider fixing range; smaller one for better fixing results • Fault-tolerance factor may vary for different applications Wei Jiang**A Basic Digital BIST Architecture**Wei Jiang**Challenges**• Analog circuitry • No convincing fault model • Difficult to identify faults • Device parameters more susceptible to process variation than digital circuitry • Fault-free behavior based on a known range of acceptable values for component parameters • Large statistical process variation effects in deep sub-micron MOSFET devices Wei Jiang**Process Variation**• Parameter variation in nanoscale process • Yield, reliability and cost • Feature size scaling down and performance improvement • Effects on digital and analog circuitry • Analog circuitry more affected by process variation • Parameter deviation severed in nanoscale process • System performance degraded when parameter deviation exceeds beyond tolerant limits Wei Jiang**Outline**• Introduction • Background • BIST Architecture for Mixed-Signal Devices • Overview of Proposed Architecture • Test of DAC/ADC • Calibration of DAC • Sigma-Delta Modulation • Polynomial Fitting Algorithm • Conclusion Wei Jiang**Resolution and Non-linearity Error**• Resolution: N-bit • Least significant bit (LSB) • Non-linearity errors • Differential non-linearity (DNL) • Integral non-linearity (INL) Wei Jiang**Non-linearity Error of ADC**• Signal values at lower and upper edges of each codes Wei Jiang**Non-linearity Error of ADC/DAC**Non-linearity error Non-linearity error Wei Jiang**Noise and SNR**Wei Jiang**Outline**• Introduction • Background • BIST Architecture for Mixed-Signal Devices • Overview of Proposed Architecture • Test of DAC/ADC • Calibration of DAC • Sigma-Delta Modulation • Polynomial Fitting Algorithm • Conclusion Wei Jiang**Typical Mixed-Signal Architecture**Wei Jiang**Mixed-Signal System Test Architecture*** F. F. Dai and C. E. Stroud, “Analog and Mixed-Signal Test Architectures,” Chapter 15, p. 722 in System-on-Chip Test Architectures: Nanometer Design for Testability, Morgan Kaufmann, 2008. Wei Jiang**Test Architecture**• Digital system • Digital I/O, digital loopback • Digital signal processor (DSP) • TPG and ORA and test control unit • Mixed-signal system • DAC and ADC, Analog loopback • Analog system • Analog circuitry • Analog signal I/O, analog I/O loopback Wei Jiang**Available Testing Approaches**• Servo-loop Method • Oscillation BIST Method • Sigma-Delta Testing Method • FFT-based Testing Method • Histogram Testing Method • Widely used for testing of on-chip ADC/DAC • Need large amount of samples and slow-gain current source • Unsuitable for high-resolution converters Wei Jiang**Outline**• Introduction • Background • BIST Architecture for Mixed-Signal Devices • Overview of Proposed Architecture • Test of DAC/ADC • Calibration of DAC • Sigma-Delta Modulation • Polynomial Fitting Algorithm • Conclusion Wei Jiang**Simplified Mixed-Signal System**Wei Jiang**Proposed Approach**Wei Jiang**Testing Components**• Analog Signal Generator (ASG) • Linear ramp signals • Sinusoidal signals • Measuring ADC (m-ADC) • High-resolution and high linearity • First-order single-bit Sigma-Delta ADC • Dithering DAC (d-DAC) • Low resolution and low cost • Output voltage: specified error-tolerant range • Polynomial evaluation unit Wei Jiang**Design of Ramp Signal Generator**ΔV+Vth ΔV I/19.5 Range: 0 v~ Vdd-ΔV I I Switch for resetting ramp Carefully chosen to make ΔV ≈ 0 Wei Jiang**Sinusoidal Testing Signal**More complex design Used for dynamic testing (non-linearity (IP3), dynamic range, harmonic distortion) Fast Fourier Transformation (FFT) by DSP required Optional in the proposed BIST approach Wei Jiang**Testing Components**• Measuring ADC (m-ADC) • First-order single-bit Sigma-Delta ADC • ENOB determined by oversampling ratio • Dithering DAC (d-DAC) • Low resolution DAC: binary-weighted • Fault-tolerance factor Wei Jiang**Outline**• Introduction • Background • BIST Architecture for Mixed-Signal Devices • Overview of Proposed Architecture • Test of DAC/ADC • Calibration of DAC • Sigma-Delta Modulation • Polynomial Fitting Algorithm • Conclusion Wei Jiang**Testing Steps**• Diagnosis of testing components • Testing of on-chip ADC using analog testing signals • Testing of on-chip DAC using embedded DSP and measuring ADC • Calibration of on-chip DAC using dithering DAC • Validation of DAC calibration results using on-chip ADC/DAC Wei Jiang**Diagnosis of Testing Components***Assume non-linearities in signal generator and d-DAC do NOT match Wei Jiang**Diagnosis of Testing Components**• ASG and m-ADC • Analog signal generated; usually linear ramp • m-ADC measures analog signals • DSP determines gain and offset of measurements • d-DAC and m-ADC • DSP makes on-chip DAC output constant 0 • DSP generates digital test patterns; usually linear ramp • m-ADC measures d-DAC outputs • DSP determines gain and offset of measurements • Only situation that fault undetected • ASG and d-DAC have exactly same non-linearity errors Wei Jiang**Testing of ADC**Similar to histogram testing method Wei Jiang**Testing of ADC**• Divided full-range of ADC codes into two equal-size sections • Sum up measurements of each section • Lower bound M(0) and upper bound M(K) are discarded because of possible out-of-range measurements Wei Jiang**Estimating Coefficients**Wei Jiang**Detailed Steps**Reset ramp testing signal generator Detect first non-zero ADC output (lower-bound of samples) Measure all subsequent samples Stop at the maximum ADC output (upper-bound of samples) DSP collects all valid measurements and start to processing data Divide measured samples into two equal-size parts Accumulate measurements of each part to obtain two sums Calculate two syndromes from two sums Calculate two estimated coefficients of the linear ramp function (Optional) Compare each measured data to estimated one from ramp function Wei Jiang**Simulation Results**DNL and INL Estimation results Wei Jiang**Other considerations**• Minimal number of samples • More samples, less quantization noise, more accurate estimation • Not all codes need to be sampled in order to reduce testing time • At least 2N-2 samples are found necessary in practice • The same idea may be used with low-frequency sinusoidal testing signals instead of ramp signal • More overhead and complexities with sinusoidal generator Wei Jiang**Testing of DAC**DSP as both TPG and ORA Wei Jiang**Test of DAC**Wei Jiang**Components**• Digital circuitry (including DSP) as BIST control unit • Test pattern generation (TPG) and output response analysis (ORA) • Measuring ADC • First-order 1-bit Sigma-Delta modulator • Digital low-pass filter • Measuring outputs of DAC-under-test • Dither DAC (not used) • Low resolution DAC • Generating correcting signal for calibration • Calibrated DAC for test of ADC-under-test • ADC Polynomial Fix (not used during testing) • Digital process to revise ADC output codes Wei Jiang**Polynomial Fitting Algorithm**• Introduced by Sunter et al. in ITC’97 and A. Roy et al. in ITC’02 • Summary: • Divide DAC transfer function into four sections • Combine function outputs of each section (S0, S1, S2, S3) • Calculate four coefficients (b0, b1, b2, b3) by easily-generated equations Wei Jiang**Third-order Polynomial**• Offset • Gain • And Harmonic Distortion Wei Jiang**Simulation Results**INL of 14-bit DAC Results of fitting polynomial Oversampling ratio for m-ADC Wei Jiang**Outline**• Introduction • Background • BIST Architecture for Mixed-Signal Devices • Overview of Proposed Architecture • Test of DAC/ADC • Calibration of DAC • Sigma-Delta Modulation • Polynomial Fitting Algorithm • Conclusion Wei Jiang**Calibration of DAC**Wei Jiang The output of calibrated DAC can be considered as linear**Dithering DAC**Estimated DAC resolution (bits) Oversampling ratio (OSR) α=1 2 3 17bits Resolution of dithering-DAC (bits) low-resolution DAC Better linearity output with DEM Must be tested by measuring ADC before test of on-chip mixed-signal devices Wei Jiang**Polynomial Evaluation**• Either hardware or software implementation • Hardware Implementation • Faster and DSP not occupied • High overhead due to huge block of digital multiply circuit • Software Implementation • DSP drives both on-chip DAC and dithering DAC with calculated value • Performance penalty Wei Jiang**Simulation Results**d-DAC errors Calibration results Wei Jiang**Verification of ADC/DAC***OPTIONAL Wei Jiang