1 / 13

Synthesis

Synthesis. Learning the different commands. Constraints. Many different constraints available to apply to design: Timing Constraints Max clock period Maximum slack Max delay (non-clocked logic) Area Constraints Max area Power Constraints Max Dynamic Power.

kathyl
Télécharger la présentation

Synthesis

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. Synthesis Learning the different commands

  2. Constraints • Many different constraints available to apply to design: • Timing Constraints • Max clock period • Maximum slack • Max delay (non-clocked logic) • Area Constraints • Max area • Power Constraints • Max Dynamic Power

  3. Order of Commands to Synthesize • First set up paths to different directories Synopsys needs • Usually accomplished by a script (similar to the ones provided) • Can also be accomplished by a special file called (.synopsys_dc.setup) which defines paths to the different libraries • This is the phase were you set your libraries, different libraries try to mimic different technologies and will have different synthesis results

  4. Synthesizing • Analyzing the files to be processed (opening your file) • The analyze command is the file which actually opens your VDHL file. • The analyze command looks through your VHDL code for any syntactical errors. • Format of analyze command is • analyze –f vhdl filename (filename should be in a path where synopsys can find it) • For multiple files can use this format • analyze –f vhdl { firstFile secondFile } • The analyze command will return a 1 if there were no errors during the analyze process

  5. Synthesizing • The next step is to elaborate your design. Elaborating the design allows Synopsys to build a circuit which represents your design in an intermediary language. • The format for the elaborate command is: • elaborate EntityNameOfDesign Or • elaborate EntityNameOfDesign –architecture ArchitectureName

  6. Synthesizing • Next we set the current design, we need to do this because it is possible that we have elaborated multiple entities • The command is simply: • current_design EntityNameOfDesign • Another command we usually want run after elaborating is the uniquify command. It is used to disambiguate between multiple instantiated hierarchies by giving each a unique name • uniquify (it just works on the current design) • This gives compiler greater flexibility in optimizing the design

  7. Synthesizing • Next we want to check for unwanted loops/latches in our designs • To check for latches we use the report_timing command (it has many options but we use the loops option) • report_timing –loops • To check for latches we use the all_registers command (it can be used in a number of ways to show the type of memory used in the design). To show latches we use the level_sensitive option • all_registers –level_sensitive • To print all flip-flops we could use the “-edge_triggered” option

  8. Synthesizing • Now we set all of our constraints, there are many possible constraints to use, some of the popular ones are: • create_clock nameOfClk –period PeriodValue • set_max_area UnitsOfArea • set_max_dynamic_power UnitsOfPower • set_operating_conditions –library LibName OperatingConditionsName • set_wire_load WireLoadSize • Used to model the interconnect effects based upon a certain die size (for example 10X10 20X20, etc)

  9. Synthesizing • Now we compile the design • Compile –map_effort LevelOfEffort • The map_effort tells the compiler how hard (and consequentially how long) it should work at trying to achieve the area constraint that was set After Compile is complete we can view the many reports that are available showing us how the compile went, however first thing to do is to check the design to make sure it compiled properly • Do this with the check_design command

  10. Reports of Synthesis • Many reports available to tell you how Synthesis went • report_constraints • Gives you many of the constraints that your design had • report_references • Gives information about the different cells used in the design, and whether or not they are shared • report_area • report_timing • report_fsm • Gives information on any Finite State Machines that were created in your design • report_attributes

  11. Synthesis • If not satisfied with results can use the ungroup command to try and remove a level of hierarchy and recompile • ungroup -all

  12. Automated Synthesis • Can actually use a script that performs synthesis in the background and can email you when complete • Sample Script below: • File called EmailScript • Contents • #!/bin/sh • dc_shell-t –f SciptName • mail –s “Your Script has Completed” YourEmail@yourServer.edu < additionalFileToAttachToEmail

  13. Automated Synthesis • So, first create script and put in your directory • Give executable permission • chmod u+x ScriptName • Extend CpuLimit • cpulimit 1000000000 • Check to make sure no one else is using machine (use the “who” command), otherwise synthesis will take longer • Call script and run in background • nohup ScriptName & (can view terminal output of program in the nohup.out file to make sure synthesis started properly) • Logout (it may hang at the logout command, this is ok just close the terminal window) • To double check script, login to same computer where script is being run and type • ps –aef | grep YourUserName • You should see a process called synopsys (may have other stuff attached) you can then see how long it has been running for

More Related